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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-05 14:21:44 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-05 14:21:44 -0700 |
| commit | fd8ef128bfdc01b6bcf90ca5a3426aac22811161 (patch) | |
| tree | ebf3ce1c2d603ff507d3d5dd08bc60b056a231c1 /passes | |
| parent | a3a80b755cb78866060f71348e2a0b14f96c574b (diff) | |
| download | yosys-fd8ef128bfdc01b6bcf90ca5a3426aac22811161.tar.gz yosys-fd8ef128bfdc01b6bcf90ca5a3426aac22811161.tar.bz2 yosys-fd8ef128bfdc01b6bcf90ca5a3426aac22811161.zip | |
Missing doc for -tech xilinx in shregmap
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/shregmap.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 75eedfbcc..21dfe9619 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -606,6 +606,9 @@ struct ShregmapPass : public Pass { log(" -tech greenpak4\n"); log(" map to greenpak4 shift registers.\n"); log("\n"); + log(" -tech xilinx\n"); + log(" map to xilinx dynamic-length shift registers.\n"); + log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { |