aboutsummaryrefslogtreecommitdiffstats
path: root/passes/techmap/techmap.cc
Commit message (Expand)AuthorAgeFilesLines
* Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-021-2/+2
|\
| * kernel: SigSpec use more const& + overloads to prevent implicit SigSpecEddie Hung2020-03-131-2/+2
* | techmap: Fix cell names with _TECHMAP_REPLACE_.*Marcin Kościelnicki2020-03-231-1/+1
|/
* Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolfEddie Hung2019-10-021-4/+8
* techmap wires named _TECHMAP_REPLACE_.<identifier> to create aliasEddie Hung2019-09-301-0/+10
* Fix _TECHMAP_REMOVEINIT_ handling.Marcin Kościelnicki2019-09-271-13/+17
* Trim mismatched connection to be same (smallest) sizeEddie Hung2019-09-201-0/+6
* Fix first testcase in #1391Eddie Hung2019-09-201-1/+1
* Add techmap_autopurge attribute, fixes #1381Clifford Wolf2019-09-191-5/+49
* techmap: Add support for extracting init values of portsMarcin Kościelnicki2019-09-071-1/+70
* Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes ...Clifford Wolf2019-09-051-8/+24
* Add flatten handling of pre-existing wires as created by interfaces, fixes #1145Clifford Wolf2019-09-051-8/+20
* GrammarEddie Hung2019-08-201-1/+1
* techmap -max_iter to apply to each module individuallyEddie Hung2019-08-201-4/+6
* Use ID::keep more liberally tooEddie Hung2019-08-151-1/+1
* Use more ID::{A,B,Y,blackbox,whitebox}Eddie Hung2019-08-151-1/+1
* ID(\\.*) -> ID(.*)Eddie Hung2019-08-151-32/+32
* Transform all "\\*" identifiers into ID()Eddie Hung2019-08-151-48/+48
* Transform "$.*" to ID("$.*") in passes/techmapEddie Hung2019-08-151-4/+4
* More use of IdString::in()Eddie Hung2019-08-151-2/+2
* substr() -> compare()Eddie Hung2019-08-071-10/+10
* stoi -> atoiEddie Hung2019-08-071-1/+1
* Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-061-1/+1
* Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zeroEddie Hung2019-07-091-0/+3
* Add log_debug() frameworkClifford Wolf2019-04-221-5/+32
* Disable blackbox detection in techmap filesClifford Wolf2019-04-221-1/+1
* Add "techmap -wb", use in formal flowsClifford Wolf2019-04-201-1/+8
* Check blackbox attribute in techmap/simplemapClifford Wolf2019-04-201-1/+1
* Ignore 'whitebox' attr in flatten with "-wb" optionEddie Hung2019-04-181-5/+19
* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-2/+2
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-4/+4
* Replace -ignore_redef with -[no]overwriteClifford Wolf2018-05-031-2/+2
* Fix handling of src attributes in flattenClifford Wolf2018-03-101-7/+2
* Add support for "yosys -E"Clifford Wolf2018-01-071-0/+1
* updated to use get_src_attribute() and set_src_attribute().Jason Lowdermilk2017-08-311-4/+2
* Add support for source line tracking through synthesis phaseJason Lowdermilk2017-08-291-0/+7
* Fix handling of empty cell port assignments (i.e. ignore them)Clifford Wolf2017-07-211-0/+3
* Copy attributes to _TECHMAP_REPLACE_ cellsClifford Wolf2017-02-161-2/+8
* Fix techmap for inout ports connected to inout portsClifford Wolf2017-02-131-2/+7
* Build fixes for VS 2015Clifford Wolf2016-10-161-1/+2
* Added MEMID handling to "flatten" passClifford Wolf2016-10-141-0/+6
* Bugfix in techmap parameter handlingClifford Wolf2016-09-141-1/+1
* Fixed preservation of important attributes in techmapClifford Wolf2016-05-061-4/+32
* Added "yosys -D" featureClifford Wolf2016-04-211-5/+5
* Fixed some visual studio warningsClifford Wolf2016-02-131-1/+1
* equiv_purge bugfix, using SigChunk in Yosys namespaceClifford Wolf2015-10-241-1/+1
* Fixed "flatten" for unconnected inout portsClifford Wolf2015-10-131-1/+1
* Another block of spelling fixesLarry Doolittle2015-08-141-1/+1
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-8/+8
* Fixed flatten $meminit handlingClifford Wolf2015-07-301-1/+1