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author | Jason Lowdermilk <jlowder@chipscan.us> | 2017-08-31 14:51:56 -0600 |
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committer | Jason Lowdermilk <jlowder@chipscan.us> | 2017-08-31 14:51:56 -0600 |
commit | 8dc6083de7c0328a8cd1d6e7b76dfd528b7baa3a (patch) | |
tree | aa6377e3fd95214735bca3b6c3fe920b78e29f08 /passes/techmap/techmap.cc | |
parent | 71d43cfc08b1949d5d07d6715107cd87c40e4465 (diff) | |
download | yosys-8dc6083de7c0328a8cd1d6e7b76dfd528b7baa3a.tar.gz yosys-8dc6083de7c0328a8cd1d6e7b76dfd528b7baa3a.tar.bz2 yosys-8dc6083de7c0328a8cd1d6e7b76dfd528b7baa3a.zip |
updated to use get_src_attribute() and set_src_attribute().
Diffstat (limited to 'passes/techmap/techmap.cc')
-rw-r--r-- | passes/techmap/techmap.cc | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index acc5d7471..d9e81e808 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -172,7 +172,6 @@ struct TechmapWorker std::string orig_cell_name; pool<string> extra_src_attrs; - std::string src = cell->attributes["\\src"].decode_string(); if (!flatten_mode) { @@ -341,7 +340,7 @@ struct TechmapWorker RTLIL::Cell *c = module->addCell(c_name, it.second); design->select(module, c); - if (!src.empty()) c->attributes["\\src"] = src; + c->set_src_attribute(cell->get_src_attribute()); if (!flatten_mode && c->type.substr(0, 2) == "\\$") c->type = c->type.substr(1); @@ -467,7 +466,6 @@ struct TechmapWorker log_assert(cell == module->cell(cell->name)); bool mapped_cell = false; - std::string src = cell->attributes["\\src"].decode_string(); std::string cell_type = cell->type.str(); if (in_recursion && cell_type.substr(0, 2) == "\\$") @@ -517,7 +515,7 @@ struct TechmapWorker extmapper_module = extmapper_design->addModule(m_name); RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell); - if (!src.empty()) extmapper_cell->attributes["\\src"] = src; + extmapper_cell->set_src_attribute(cell->get_src_attribute()); int port_counter = 1; for (auto &c : extmapper_cell->connections_) { |