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* Merge pull request #1085 from YosysHQ/eddie/shregmap_improveEddie Hung2019-06-211-3/+15
|\ | | | | Improve shregmap to handle case where first flop is common to two chains
| * Actually, there might not be any harm in updating sigmap...Eddie Hung2019-06-201-3/+1
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| * Add comment as per @cliffordwolfEddie Hung2019-06-201-0/+11
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| * Revert "Try way that doesn't involve creating a new wire"Eddie Hung2019-06-111-15/+10
| | | | | | | | This reverts commit 2f427acc9ed23c77e89386f4fbf53ac580bf0f0b.
| * Try way that doesn't involve creating a new wireEddie Hung2019-06-111-10/+15
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| * If d_bit already in sigbit_chain_next, create extra wireEddie Hung2019-06-101-3/+6
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* | Improve shregmap help message, fixes #1113Clifford Wolf2019-06-201-0/+2
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Missing doc for -tech xilinx in shregmapEddie Hung2019-06-051-0/+3
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* Copy with 1'bx padding in $shiftxEddie Hung2019-04-281-1/+11
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* Use new pmux2shiftx from #944, remove my old attemptEddie Hung2019-04-211-52/+0
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* $_XILINX_SHREG_ to preserve src attributeEddie Hung2019-04-081-0/+1
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* Cope with undoing #895Eddie Hung2019-04-081-14/+26
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* Revert "Remove handling for $pmux, since #895"Eddie Hung2019-04-081-0/+40
| | | | This reverts commit aa693d5723ef1438d42cd35a26673703b1eff79f.
* Call shregmap twice -- once for variable, another for fixedEddie Hung2019-04-051-29/+17
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* Remove handling for $pmux, since #895Eddie Hung2019-04-031-40/+0
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* Cope with SHREG not having E port; Revert $pmux fine tuneEddie Hung2019-03-231-4/+3
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* Add support for SHREGMAP+$mux, also fine tune $pmuxEddie Hung2019-03-221-1/+24
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* Leftover printfEddie Hung2019-03-221-1/+0
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* Fixes for multibitEddie Hung2019-03-221-18/+38
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* Working for 1 bitEddie Hung2019-03-221-11/+49
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* OptEddie Hung2019-03-211-1/+1
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* Fix spacingEddie Hung2019-03-201-239/+239
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* Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable lengthEddie Hung2019-03-191-5/+14
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* Add support for variable length Xilinx SRL > 128Eddie Hung2019-03-191-6/+0
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* shregmap -tech xilinx to delete $shiftx for var length SRLEddie Hung2019-03-191-10/+3
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* Make output port a non chain userEddie Hung2019-03-191-2/+4
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* Fix shregmap to correctly recognise non chain users; cleanupEddie Hung2019-03-181-17/+15
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* shiftx NULL pointer checkEddie Hung2019-03-181-8/+10
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* CleanupEddie Hung2019-03-161-35/+25
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* Only accept <128 for variable length, only if $shiftx exclusiveEddie Hung2019-03-161-8/+17
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* WorkingEddie Hung2019-03-151-227/+356
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* Revert "Add shregmap -init_msb_first and use in synth_xilinx"Eddie Hung2019-03-141-14/+2
| | | | This reverts commit 26ecbc1aee1dca1c186ab2b51835d74f67bc3e75.
* Add shregmap -init_msb_first and use in synth_xilinxEddie Hung2019-03-141-2/+14
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* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Added support for "keep" attribute to shregmapClifford Wolf2016-05-071-2/+2
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* Changed port names in greenpak shregmapAndrew Zonenberg2016-05-041-1/+1
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* Improvements in greenpak4 shreg mappingClifford Wolf2016-04-231-16/+35
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* Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-04-231-0/+1
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| * Added "shregmap -zinit" for greenpak4 techClifford Wolf2016-04-231-0/+1
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* | Fixed typo in help textAndrew Zonenberg2016-04-221-1/+1
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* Added "shregmap -tech greenpak4"Clifford Wolf2016-04-221-6/+97
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* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
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* Added "shregmap -params"Clifford Wolf2016-04-181-4/+43
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* Added "shregmap -zinit" and "shregmap -init"Clifford Wolf2016-04-181-2/+65
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* Improvements in "shregmap"Clifford Wolf2016-04-171-30/+140
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* Added "shregmap" passClifford Wolf2016-04-161-0/+261