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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 13:08:43 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 13:08:43 -0700 |
| commit | 0ea7eba5f13b20de28181a66181ee821820027db (patch) | |
| tree | 9792695f99ef88ae4d119104f8106c06a91caedb /passes/techmap/shregmap.cc | |
| parent | ed32119d133166c78870137c6ce3db781b92c2e4 (diff) | |
| download | yosys-0ea7eba5f13b20de28181a66181ee821820027db.tar.gz yosys-0ea7eba5f13b20de28181a66181ee821820027db.tar.bz2 yosys-0ea7eba5f13b20de28181a66181ee821820027db.zip | |
Make output port a non chain user
Diffstat (limited to 'passes/techmap/shregmap.cc')
| -rw-r--r-- | passes/techmap/shregmap.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index d95cadde5..3b3170e04 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -118,7 +118,7 @@ struct ShregmapTechXilinx7 : ShregmapTech auto it = sigbit_to_shiftx_offset.find(bit); if (it == sigbit_to_shiftx_offset.end()) return; - if (cell->type == "$shiftx" && port == "\\A") + if (cell && cell->type == "$shiftx" && port == "\\A") return; sigbit_to_shiftx_offset.erase(it); } @@ -228,8 +228,10 @@ struct ShregmapWorker for (auto wire : module->wires()) { if (wire->port_output || wire->get_bool_attribute("\\keep")) { - for (auto bit : sigmap(wire)) + for (auto bit : sigmap(wire)) { sigbit_with_non_chain_users.insert(bit); + if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {}); + } } if (wire->attributes.count("\\init")) { |