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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-21 10:20:27 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-21 10:20:27 -0700 |
| commit | 5597270b9e2331d8836c8c24a073aadc1e19584a (patch) | |
| tree | 839eed4d7a1157550130a38af3250f0a46cd13ef /passes/techmap/shregmap.cc | |
| parent | 2b911e270ba8012aa85f342838ed31b54568f257 (diff) | |
| download | yosys-5597270b9e2331d8836c8c24a073aadc1e19584a.tar.gz yosys-5597270b9e2331d8836c8c24a073aadc1e19584a.tar.bz2 yosys-5597270b9e2331d8836c8c24a073aadc1e19584a.zip | |
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Diffstat (limited to 'passes/techmap/shregmap.cc')
| -rw-r--r-- | passes/techmap/shregmap.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 028f4ba35..d5221d46f 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -102,7 +102,7 @@ struct ShregmapTechXilinx7 : ShregmapTech virtual void init(const Module* module, const SigMap &sigmap) override { - for (auto i : module->cells_) { + for (const auto &i : module->cells_) { auto cell = i.second; if (cell->type != "$shiftx") continue; if (cell->getParam("\\Y_WIDTH") != 1) continue; |