iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge pull request #1085 from YosysHQ/eddie/shregmap_improve	Eddie Hung	2019-06-21	1	-3/+15
\|\
\| *	Actually, there might not be any harm in updating sigmap...	Eddie Hung	2019-06-20	1	-3/+1
\| *	Add comment as per @cliffordwolf	Eddie Hung	2019-06-20	1	-0/+11
\| *	Revert "Try way that doesn't involve creating a new wire"	Eddie Hung	2019-06-11	1	-15/+10
\| *	Try way that doesn't involve creating a new wire	Eddie Hung	2019-06-11	1	-10/+15
\| *	If d_bit already in sigbit_chain_next, create extra wire	Eddie Hung	2019-06-10	1	-3/+6
* \|	Improve shregmap help message, fixes #1113	Clifford Wolf	2019-06-20	1	-0/+2
\|/
*	Missing doc for -tech xilinx in shregmap	Eddie Hung	2019-06-05	1	-0/+3
*	Copy with 1'bx padding in $shiftx	Eddie Hung	2019-04-28	1	-1/+11
*	Use new pmux2shiftx from #944, remove my old attempt	Eddie Hung	2019-04-21	1	-52/+0
*	$_XILINX_SHREG_ to preserve src attribute	Eddie Hung	2019-04-08	1	-0/+1
*	Cope with undoing #895	Eddie Hung	2019-04-08	1	-14/+26
*	Revert "Remove handling for $pmux, since #895"	Eddie Hung	2019-04-08	1	-0/+40
*	Call shregmap twice -- once for variable, another for fixed	Eddie Hung	2019-04-05	1	-29/+17
*	Remove handling for $pmux, since #895	Eddie Hung	2019-04-03	1	-40/+0
*	Cope with SHREG not having E port; Revert $pmux fine tune	Eddie Hung	2019-03-23	1	-4/+3
*	Add support for SHREGMAP+$mux, also fine tune $pmux	Eddie Hung	2019-03-22	1	-1/+24
*	Leftover printf	Eddie Hung	2019-03-22	1	-1/+0
*	Fixes for multibit	Eddie Hung	2019-03-22	1	-18/+38
*	Working for 1 bit	Eddie Hung	2019-03-22	1	-11/+49
*	Opt	Eddie Hung	2019-03-21	1	-1/+1
*	Fix spacing	Eddie Hung	2019-03-20	1	-239/+239
*	Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length	Eddie Hung	2019-03-19	1	-5/+14
*	Add support for variable length Xilinx SRL > 128	Eddie Hung	2019-03-19	1	-6/+0
*	shregmap -tech xilinx to delete $shiftx for var length SRL	Eddie Hung	2019-03-19	1	-10/+3
*	Make output port a non chain user	Eddie Hung	2019-03-19	1	-2/+4
*	Fix shregmap to correctly recognise non chain users; cleanup	Eddie Hung	2019-03-18	1	-17/+15
*	shiftx NULL pointer check	Eddie Hung	2019-03-18	1	-8/+10
*	Cleanup	Eddie Hung	2019-03-16	1	-35/+25
*	Only accept <128 for variable length, only if $shiftx exclusive	Eddie Hung	2019-03-16	1	-8/+17
*	Working	Eddie Hung	2019-03-15	1	-227/+356
*	Revert "Add shregmap -init_msb_first and use in synth_xilinx"	Eddie Hung	2019-03-14	1	-14/+2
*	Add shregmap -init_msb_first and use in synth_xilinx	Eddie Hung	2019-03-14	1	-2/+14
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Added support for "keep" attribute to shregmap	Clifford Wolf	2016-05-07	1	-2/+2
*	Changed port names in greenpak shregmap	Andrew Zonenberg	2016-05-04	1	-1/+1
*	Improvements in greenpak4 shreg mapping	Clifford Wolf	2016-04-23	1	-16/+35
*	Merge https://github.com/cliffordwolf/yosys	Andrew Zonenberg	2016-04-23	1	-0/+1
\|\
\| *	Added "shregmap -zinit" for greenpak4 tech	Clifford Wolf	2016-04-23	1	-0/+1
* \|	Fixed typo in help text	Andrew Zonenberg	2016-04-22	1	-1/+1
\|/
*	Added "shregmap -tech greenpak4"	Clifford Wolf	2016-04-22	1	-6/+97
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Added "shregmap -params"	Clifford Wolf	2016-04-18	1	-4/+43
*	Added "shregmap -zinit" and "shregmap -init"	Clifford Wolf	2016-04-18	1	-2/+65
*	Improvements in "shregmap"	Clifford Wolf	2016-04-17	1	-30/+140
*	Added "shregmap" pass	Clifford Wolf	2016-04-16	1	-0/+261