Working

1 files changed, 356 insertions, 227 deletions

diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
index f20863ba0..4b8f8a828 100644
--- a/passes/techmap/shregmap.cc
+++ b/passes/techmap/shregmap.cc
@@ -26,7 +26,9 @@ PRIVATE_NAMESPACE_BEGIN
 struct ShregmapTech
 {
 	virtual ~ShregmapTech() { }
-	virtual bool analyze(vector<int> &taps) = 0;
+	virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {}
+	virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {}
+	virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) = 0;
 	virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) = 0;
 };
 
@@ -54,7 +56,7 @@ struct ShregmapOptions
 
 struct ShregmapTechGreenpak4 : ShregmapTech
 {
-	bool analyze(vector<int> &taps)
+	bool analyze(vector<int> &taps, const vector<SigBit> &/*qbits*/)
 	{
 		if (GetSize(taps) > 2 && taps[0] == 0 && taps[2] < 17) {
 			taps.clear();
@@ -91,302 +93,423 @@ struct ShregmapTechGreenpak4 : ShregmapTech
 	}
 };
 
-struct ShregmapWorker
+struct ShregmapTechXilinx7 : ShregmapTech
 {
-	Module *module;
-	SigMap sigmap;
-
+	dict<SigBit, Cell*> sigbit_to_shiftx;
 	const ShregmapOptions &opts;
-	int dff_count, shreg_count;
 
-	pool<Cell*> remove_cells;
-	pool<SigBit> remove_init;
+	ShregmapTechXilinx7(const ShregmapOptions &opts) : opts(opts) {}
 
-	dict<SigBit, bool> sigbit_init;
-	dict<SigBit, Cell*> sigbit_chain_next;
-	dict<SigBit, Cell*> sigbit_chain_prev;
-	pool<SigBit> sigbit_with_non_chain_users;
-	pool<Cell*> chain_start_cells;
+	virtual void init(const Module* module, const SigMap &sigmap) override
+	{
+		for (auto i : module->cells_) {
+			auto cell = i.second;
+			if (cell->type != "$shiftx") continue;
+			if (cell->getParam("\\Y_WIDTH") != 1) continue;
+			for (auto bit : sigmap(cell->getPort("\\A")))
+				sigbit_to_shiftx[bit] = cell;
+		}
+	}
 
-	void make_sigbit_chain_next_prev()
+	virtual void non_chain_user(const SigBit &bit, const Cell *cell, IdString port) override
 	{
-		for (auto wire : module->wires())
-		{
-			if (wire->port_output || wire->get_bool_attribute("\\keep")) {
-				for (auto bit : sigmap(wire))
-					sigbit_with_non_chain_users.insert(bit);
-			}
+		auto it = sigbit_to_shiftx.find(bit);
+		if (it == sigbit_to_shiftx.end())
+			return;
+		if (cell->type == "$shiftx" && port == "\\A")
+			return;
+		it->second = nullptr;
+	}
 
-			if (wire->attributes.count("\\init")) {
-				SigSpec initsig = sigmap(wire);
-				Const initval = wire->attributes.at("\\init");
-				for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
-					if (initval[i] == State::S0 && !opts.zinit)
-						sigbit_init[initsig[i]] = false;
-					else if (initval[i] == State::S1)
-						sigbit_init[initsig[i]] = true;
-			}
-		}
+	virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) override
+	{
+		if (GetSize(taps) == 1)
+			return taps[0] >= opts.minlen-1;
 
-		for (auto cell : module->cells())
-		{
-			if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute("\\keep"))
-			{
-				IdString d_port = opts.ffcells.at(cell->type).first;
-				IdString q_port = opts.ffcells.at(cell->type).second;
-
-				SigBit d_bit = sigmap(cell->getPort(d_port).as_bit());
-				SigBit q_bit = sigmap(cell->getPort(q_port).as_bit());
-
-				if (opts.init || sigbit_init.count(q_bit) == 0)
-				{
-					if (sigbit_chain_next.count(d_bit)) {
-						sigbit_with_non_chain_users.insert(d_bit);
-					} else
-						sigbit_chain_next[d_bit] = cell;
-
-					sigbit_chain_prev[q_bit] = cell;
-					continue;
+		if (taps.back() < opts.minlen-1)
+			return false;
+
+		Cell *shiftx = nullptr;
+		int offset = 0;
+		for (int i = 0; i < GetSize(taps); ++i) {
+			// Check taps are sequential
+			if (i != taps[i])
+				return false;
+			// Check taps are not connected to a shift register,
+			// or sequential to the same shift register
+			auto it = sigbit_to_shiftx.find(qbits[i]);
+			if (i == 0) {
+				if (it != sigbit_to_shiftx.end()) {
+					shiftx = it->second;
+					// NULL indicates there are non-shiftx users
+					if (shiftx == nullptr)
+						return false;
+					offset = qbits[i].offset;
+				}
+			}
+			else {
+				if (it == sigbit_to_shiftx.end()) {
+					if (shiftx != nullptr)
+						return false;
+				}
+				else {
+					if (shiftx != it->second)
+						return false;
+					if (qbits[i].offset != offset + i)
+						return false;
 				}
 			}
-
-			for (auto conn : cell->connections())
-				if (cell->input(conn.first))
-					for (auto bit : sigmap(conn.second))
-						sigbit_with_non_chain_users.insert(bit);
 		}
+
+		return true;
 	}
 
-	void find_chain_start_cells()
+	virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) override
 	{
-		for (auto it : sigbit_chain_next)
-		{
-			if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first))
-				goto start_cell;
+		const auto &tap = *taps.begin();
+		auto bit = tap.second;
+		auto it = sigbit_to_shiftx.find(bit);
+		if (it == sigbit_to_shiftx.end())
+			return true;
 
-			if (sigbit_chain_prev.count(it.first) != 0)
-			{
-				Cell *c1 = sigbit_chain_prev.at(it.first);
-				Cell *c2 = it.second;
+		Cell* shiftx = it->second;
 
-				if (c1->type != c2->type)
-					goto start_cell;
+		auto module = cell->module;
 
-				if (c1->parameters != c2->parameters)
-					goto start_cell;
+		auto cell_q = cell->getPort("\\Q").as_bit();
 
-				IdString d_port = opts.ffcells.at(c1->type).first;
-				IdString q_port = opts.ffcells.at(c1->type).second;
+		auto shiftx_a = shiftx->getPort("\\A").bits();
+		int offset = 0;
+		for (auto bit : shiftx_a) {
+			if (bit == cell_q)
+				break;
+			++offset;
+		}
+		offset -= taps.size() - 1;
+		log_assert(offset >= 0);
+		for (size_t i = offset; i < offset + taps.size(); ++i)
+			shiftx_a[i] = cell_q;
+		// FIXME: Hack to ensure that $shiftx gets optimised away
+		//   Without this, Yosys will refuse to optimise away a $shiftx
+		//   where \\A 's width is not perfectly \\B_WIDTH ** 2
+		auto shiftx_bwidth = shiftx->getParam("\\B_WIDTH").as_int();
+		shiftx_a.resize(1 << shiftx_bwidth, shiftx_a.back());
+		shiftx->setPort("\\A", shiftx_a);
+		shiftx->setParam("\\A_WIDTH", shiftx_a.size());
+
+		auto length = module->addWire(NEW_ID, ceil(log2(taps.size())));
+		module->addSub(NEW_ID, shiftx->getPort("\\B"), RTLIL::Const(offset, ceil(log2(offset))), length);
+		cell->setPort("\\L", length);
 
-				auto c1_conn = c1->connections();
-				auto c2_conn = c1->connections();
 
-				c1_conn.erase(d_port);
-				c1_conn.erase(q_port);
+		return true;
+	}
+};
 
-				c2_conn.erase(d_port);
-				c2_conn.erase(q_port);
 
-				if (c1_conn != c2_conn)
-					goto start_cell;
+struct ShregmapWorker
+{
+    Module *module;
+    SigMap sigmap;
 
-				continue;
-			}
+    const ShregmapOptions &opts;
+    int dff_count, shreg_count;
 
-		start_cell:
-			chain_start_cells.insert(it.second);
-		}
-	}
+    pool<Cell*> remove_cells;
+    pool<SigBit> remove_init;
+
+    dict<SigBit, bool> sigbit_init;
+    dict<SigBit, Cell*> sigbit_chain_next;
+    dict<SigBit, Cell*> sigbit_chain_prev;
+    pool<SigBit> sigbit_with_non_chain_users;
+    pool<Cell*> chain_start_cells;
 
-	vector<Cell*> create_chain(Cell *start_cell)
+    void make_sigbit_chain_next_prev()
+    {
+	for (auto wire : module->wires())
 	{
-		vector<Cell*> chain;
+	    if (wire->port_output || wire->get_bool_attribute("\\keep")) {
+		for (auto bit : sigmap(wire))
+		    sigbit_with_non_chain_users.insert(bit);
+	    }
+
+	    if (wire->attributes.count("\\init")) {
+		SigSpec initsig = sigmap(wire);
+		Const initval = wire->attributes.at("\\init");
+		for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
+		    if (initval[i] == State::S0 && !opts.zinit)
+			sigbit_init[initsig[i]] = false;
+		    else if (initval[i] == State::S1)
+			sigbit_init[initsig[i]] = true;
+	    }
+	}
 
-		Cell *c = start_cell;
-		while (c != nullptr)
-		{
-			chain.push_back(c);
+	for (auto cell : module->cells())
+	{
+	    if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute("\\keep"))
+	    {
+		IdString d_port = opts.ffcells.at(cell->type).first;
+		IdString q_port = opts.ffcells.at(cell->type).second;
 
-			IdString q_port = opts.ffcells.at(c->type).second;
-			SigBit q_bit = sigmap(c->getPort(q_port).as_bit());
+		SigBit d_bit = sigmap(cell->getPort(d_port).as_bit());
+		SigBit q_bit = sigmap(cell->getPort(q_port).as_bit());
 
-			if (sigbit_chain_next.count(q_bit) == 0)
-				break;
+		if (opts.init || sigbit_init.count(q_bit) == 0)
+		{
+		    if (sigbit_chain_next.count(d_bit)) {
+			sigbit_with_non_chain_users.insert(d_bit);
+		    } else
+			sigbit_chain_next[d_bit] = cell;
 
-			c = sigbit_chain_next.at(q_bit);
-			if (chain_start_cells.count(c) != 0)
-				break;
+		    sigbit_chain_prev[q_bit] = cell;
+		    continue;
 		}
-
-		return chain;
+	    }
+
+	    for (auto conn : cell->connections())
+		if (cell->input(conn.first))
+		    for (auto bit : sigmap(conn.second)) {
+			sigbit_with_non_chain_users.insert(bit);
+			if (opts.tech) opts.tech->non_chain_user(bit, cell, conn.first);
+		    }
 	}
+    }
 
-	void process_chain(vector<Cell*> &chain)
+    void find_chain_start_cells()
+    {
+	for (auto it : sigbit_chain_next)
 	{
-		if (GetSize(chain) < opts.keep_before + opts.minlen + opts.keep_after)
-			return;
+	    if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first))
+		goto start_cell;
 
-		int cursor = opts.keep_before;
-		while (cursor < GetSize(chain) - opts.keep_after)
-		{
-			int depth = GetSize(chain) - opts.keep_after - cursor;
+	    if (sigbit_chain_prev.count(it.first) != 0)
+	    {
+		Cell *c1 = sigbit_chain_prev.at(it.first);
+		Cell *c2 = it.second;
 
-			if (opts.maxlen > 0)
-				depth = std::min(opts.maxlen, depth);
+		if (c1->type != c2->type)
+		    goto start_cell;
 
-			Cell *first_cell = chain[cursor];
-			IdString q_port = opts.ffcells.at(first_cell->type).second;
-			dict<int, SigBit> taps_dict;
+		if (c1->parameters != c2->parameters)
+		    goto start_cell;
 
-			if (opts.tech)
-			{
-				vector<SigBit> qbits;
-				vector<int> taps;
+		IdString d_port = opts.ffcells.at(c1->type).first;
+		IdString q_port = opts.ffcells.at(c1->type).second;
 
-				for (int i = 0; i < depth; i++)
-				{
-					Cell *cell = chain[cursor+i];
-					auto qbit = sigmap(cell->getPort(q_port));
-					qbits.push_back(qbit);
+		auto c1_conn = c1->connections();
+		auto c2_conn = c1->connections();
 
-					if (sigbit_with_non_chain_users.count(qbit))
-						taps.push_back(i);
-				}
-
-				while (depth > 0)
-				{
-					if (taps.empty() || taps.back() < depth-1)
-						taps.push_back(depth-1);
+		c1_conn.erase(d_port);
+		c1_conn.erase(q_port);
 
-					if (opts.tech->analyze(taps))
-						break;
+		c2_conn.erase(d_port);
+		c2_conn.erase(q_port);
 
-					taps.pop_back();
-					depth--;
-				}
+		if (c1_conn != c2_conn)
+		    goto start_cell;
 
-				depth = 0;
-				for (auto tap : taps) {
-					taps_dict[tap] = qbits.at(tap);
-					log_assert(depth < tap+1);
-					depth = tap+1;
-				}
-			}
+		continue;
+	    }
 
-			if (depth < 2) {
-				cursor++;
-				continue;
-			}
+start_cell:
+	    chain_start_cells.insert(it.second);
+	}
+    }
 
-			Cell *last_cell = chain[cursor+depth-1];
+    vector<Cell*> create_chain(Cell *start_cell)
+    {
+	vector<Cell*> chain;
 
-			log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n",
-				log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), depth);
+	Cell *c = start_cell;
+	while (c != nullptr)
+	{
+	    chain.push_back(c);
 
-			dff_count += depth;
-			shreg_count += 1;
+	    IdString q_port = opts.ffcells.at(c->type).second;
+	    SigBit q_bit = sigmap(c->getPort(q_port).as_bit());
 
-			string shreg_cell_type_str = "$__SHREG";
-			if (opts.params) {
-				shreg_cell_type_str += "_";
-			} else {
-				if (first_cell->type[1] != '_')
-					shreg_cell_type_str += "_";
-				shreg_cell_type_str += first_cell->type.substr(1);
-			}
+	    if (sigbit_chain_next.count(q_bit) == 0)
+		break;
 
-			if (opts.init) {
-				vector<State> initval;
-				for (int i = depth-1; i >= 0; i--) {
-					SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
-					if (sigbit_init.count(bit) == 0)
-						initval.push_back(State::Sx);
-					else if (sigbit_init.at(bit))
-						initval.push_back(State::S1);
-					else
-						initval.push_back(State::S0);
-					remove_init.insert(bit);
-				}
-				first_cell->setParam("\\INIT", initval);
-			}
+	    c = sigbit_chain_next.at(q_bit);
+	    if (chain_start_cells.count(c) != 0)
+		break;
+	}
 
-			if (opts.zinit)
-				for (int i = depth-1; i >= 0; i--) {
-					SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
-					remove_init.insert(bit);
-				}
+	return chain;
+    }
 
-			if (opts.params)
-			{
-				int param_clkpol = -1;
-				int param_enpol = 2;
+    void process_chain(vector<Cell*> &chain)
+    {
+	if (GetSize(chain) < opts.keep_before + opts.minlen + opts.keep_after)
+	    return;
 
-				if (first_cell->type == "$_DFF_N_") param_clkpol = 0;
-				if (first_cell->type == "$_DFF_P_") param_clkpol = 1;
+	int cursor = opts.keep_before;
+	while (cursor < GetSize(chain) - opts.keep_after)
+	{
+	    int depth = GetSize(chain) - opts.keep_after - cursor;
 
-				if (first_cell->type == "$_DFFE_NN_") param_clkpol = 0, param_enpol = 0;
-				if (first_cell->type == "$_DFFE_NP_") param_clkpol = 0, param_enpol = 1;
-				if (first_cell->type == "$_DFFE_PN_") param_clkpol = 1, param_enpol = 0;
-				if (first_cell->type == "$_DFFE_PP_") param_clkpol = 1, param_enpol = 1;
+	    if (opts.maxlen > 0)
+		depth = std::min(opts.maxlen, depth);
 
-				log_assert(param_clkpol >= 0);
-				first_cell->setParam("\\CLKPOL", param_clkpol);
-				if (opts.ffe) first_cell->setParam("\\ENPOL", param_enpol);
-			}
+	    Cell *first_cell = chain[cursor];
+	    IdString q_port = opts.ffcells.at(first_cell->type).second;
+	    dict<int, SigBit> taps_dict;
 
-			first_cell->type = shreg_cell_type_str;
-			first_cell->setPort(q_port, last_cell->getPort(q_port));
-			first_cell->setParam("\\DEPTH", depth);
+	    if (opts.tech)
+	    {
+		vector<SigBit> qbits;
+		vector<int> taps;
 
-			if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
-				remove_cells.insert(first_cell);
+		for (int i = 0; i < depth; i++)
+		{
+		    Cell *cell = chain[cursor+i];
+		    auto qbit = sigmap(cell->getPort(q_port));
+		    qbits.push_back(qbit);
 
-			for (int i = 1; i < depth; i++)
-				remove_cells.insert(chain[cursor+i]);
-			cursor += depth;
+		    if (sigbit_with_non_chain_users.count(qbit))
+			taps.push_back(i);
 		}
-	}
 
-	void cleanup()
-	{
-		for (auto cell : remove_cells)
-			module->remove(cell);
-
-		for (auto wire : module->wires())
+		while (depth > 0)
 		{
-			if (wire->attributes.count("\\init") == 0)
-				continue;
+		    if (taps.empty() || taps.back() < depth-1)
+			taps.push_back(depth-1);
 
-			SigSpec initsig = sigmap(wire);
-			Const &initval = wire->attributes.at("\\init");
+		    if (opts.tech->analyze(taps, qbits))
+			break;
+
+		    taps.pop_back();
+		    depth--;
+		}
 
-			for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
-				if (remove_init.count(initsig[i]))
-					initval[i] = State::Sx;
+		depth = 0;
+		for (auto tap : taps) {
+		    taps_dict[tap] = qbits.at(tap);
+		    log_assert(depth < tap+1);
+		    depth = tap+1;
+		}
+	    }
+
+	    if (depth < 2) {
+		cursor++;
+		continue;
+	    }
+
+	    Cell *last_cell = chain[cursor+depth-1];
+
+	    log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n",
+		    log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), depth);
+
+	    dff_count += depth;
+	    shreg_count += 1;
+
+	    string shreg_cell_type_str = "$__SHREG";
+	    if (opts.params) {
+		shreg_cell_type_str += "_";
+	    } else {
+		if (first_cell->type[1] != '_')
+		    shreg_cell_type_str += "_";
+		shreg_cell_type_str += first_cell->type.substr(1);
+	    }
+
+	    if (opts.init) {
+		vector<State> initval;
+		for (int i = depth-1; i >= 0; i--) {
+		    SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
+		    if (sigbit_init.count(bit) == 0)
+			initval.push_back(State::Sx);
+		    else if (sigbit_init.at(bit))
+			initval.push_back(State::S1);
+		    else
+			initval.push_back(State::S0);
+		    remove_init.insert(bit);
+		}
+		first_cell->setParam("\\INIT", initval);
+	    }
 
-			if (SigSpec(initval).is_fully_undef())
-				wire->attributes.erase("\\init");
+	    if (opts.zinit)
+		for (int i = depth-1; i >= 0; i--) {
+		    SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
+		    remove_init.insert(bit);
 		}
 
-		remove_cells.clear();
-		sigbit_chain_next.clear();
-		sigbit_chain_prev.clear();
-		chain_start_cells.clear();
+	    if (opts.params)
+	    {
+		int param_clkpol = -1;
+		int param_enpol = 2;
+
+		if (first_cell->type == "$_DFF_N_") param_clkpol = 0;
+		if (first_cell->type == "$_DFF_P_") param_clkpol = 1;
+
+		if (first_cell->type == "$_DFFE_NN_") param_clkpol = 0, param_enpol = 0;
+		if (first_cell->type == "$_DFFE_NP_") param_clkpol = 0, param_enpol = 1;
+		if (first_cell->type == "$_DFFE_PN_") param_clkpol = 1, param_enpol = 0;
+		if (first_cell->type == "$_DFFE_PP_") param_clkpol = 1, param_enpol = 1;
+
+		log_assert(param_clkpol >= 0);
+		first_cell->setParam("\\CLKPOL", param_clkpol);
+		if (opts.ffe) first_cell->setParam("\\ENPOL", param_enpol);
+	    }
+
+	    first_cell->type = shreg_cell_type_str;
+	    first_cell->setPort(q_port, last_cell->getPort(q_port));
+	    if (!first_cell->hasPort("\\L"))
+		    first_cell->setPort("\\L", depth-1);
+	    first_cell->setParam("\\DEPTH", depth);
+
+	    if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
+		remove_cells.insert(first_cell);
+
+	    for (int i = 1; i < depth; i++)
+		remove_cells.insert(chain[cursor+i]);
+	    cursor += depth;
 	}
+    }
+
+    void cleanup()
+    {
+	for (auto cell : remove_cells)
+	    module->remove(cell);
 
-	ShregmapWorker(Module *module, const ShregmapOptions &opts) :
-			module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0)
+	for (auto wire : module->wires())
 	{
-		make_sigbit_chain_next_prev();
-		find_chain_start_cells();
+	    if (wire->attributes.count("\\init") == 0)
+		continue;
 
-		for (auto c : chain_start_cells) {
-			vector<Cell*> chain = create_chain(c);
-			process_chain(chain);
-		}
+	    SigSpec initsig = sigmap(wire);
+	    Const &initval = wire->attributes.at("\\init");
 
-		cleanup();
+	    for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
+		if (remove_init.count(initsig[i]))
+		    initval[i] = State::Sx;
+
+	    if (SigSpec(initval).is_fully_undef())
+		wire->attributes.erase("\\init");
 	}
+
+	remove_cells.clear();
+	sigbit_chain_next.clear();
+	sigbit_chain_prev.clear();
+	chain_start_cells.clear();
+    }
+
+    ShregmapWorker(Module *module, const ShregmapOptions &opts) :
+	module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0)
+    {
+	if (opts.tech)
+	    opts.tech->init(module, sigmap);
+
+	make_sigbit_chain_next_prev();
+	find_chain_start_cells();
+
+	for (auto c : chain_start_cells) {
+	    vector<Cell*> chain = create_chain(c);
+	    process_chain(chain);
+	}
+
+	cleanup();
+    }
 };
 
 struct ShregmapPass : public Pass {
@@ -501,6 +624,12 @@ struct ShregmapPass : public Pass {
 					clkpol = "pos";
 					opts.zinit = true;
 					opts.tech = new ShregmapTechGreenpak4;
+				}
+				else if (tech == "xilinx") {
+					opts.init = true;
+					opts.params = true;
+					enpol = "any_or_none";
+					opts.tech = new ShregmapTechXilinx7(opts);
 				} else {
 					argidx--;
 					break;