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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-23 16:09:38 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-23 16:09:38 -0700 |
| commit | bf83c074c82756b1cd23a9c3998b6c4d535dae29 (patch) | |
| tree | bdbcb2c398a3a1679d1201c7cf4ac63c2e9089ad /passes/techmap/shregmap.cc | |
| parent | 098bd5758fe2e4cb7efa44503a1c498b0a2ace5e (diff) | |
| download | yosys-bf83c074c82756b1cd23a9c3998b6c4d535dae29.tar.gz yosys-bf83c074c82756b1cd23a9c3998b6c4d535dae29.tar.bz2 yosys-bf83c074c82756b1cd23a9c3998b6c4d535dae29.zip | |
Cope with SHREG not having E port; Revert $pmux fine tune
Diffstat (limited to 'passes/techmap/shregmap.cc')
| -rw-r--r-- | passes/techmap/shregmap.cc | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index fb48094ec..7cf52c19a 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -240,7 +240,8 @@ struct ShregmapTechXilinx7 : ShregmapTech newcell->setPort("\\C", cell->getPort("\\C")); newcell->setPort("\\D", cell->getPort("\\D")); - newcell->setPort("\\E", cell->getPort("\\E")); + if (cell->hasPort("\\E")) + newcell->setPort("\\E", cell->getPort("\\E")); Cell* shiftx = std::get<0>(it->second); RTLIL::SigSpec l_wire, q_wire; @@ -257,10 +258,8 @@ struct ShregmapTechXilinx7 : ShregmapTech RTLIL::SigSpec b_port; for (int i = shiftx->getParam("\\S_WIDTH").as_int(); i > 0; i--) b_port.append(RTLIL::Const(i, clog2taps)); - for (int i = (1 << clog2taps); i > shiftx->getParam("\\S_WIDTH").as_int(); i--) - b_port.append(RTLIL::Const(RTLIL::Sx, clog2taps)); l_wire = cell->module->addWire(NEW_ID, clog2taps); - RTLIL::SigSpec s_wire = cell->module->addWire(NEW_ID, (1 << clog2taps)); + RTLIL::SigSpec s_wire = cell->module->addWire(NEW_ID, shiftx->getParam("\\S_WIDTH").as_int()); cell->module->connect(s_wire.extract(0, shiftx->getParam("\\S_WIDTH").as_int()), shiftx->getPort("\\S")); cell->module->addPmux(NEW_ID, RTLIL::Const(0, clog2taps), b_port, s_wire, l_wire); int group = std::get<2>(it->second); |