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Author
Age
Files
Lines
*
clk2fflogic: Generate less unused logic when using verific
Jannis Harder
2022-08-16
1
-1
/
+4
*
formalff: New -setundef option
Jannis Harder
2022-08-16
1
-0
/
+335
*
formalff: Set new replaced_by_gclk attribute on removed dff's clks
Jannis Harder
2022-08-16
1
-0
/
+22
*
Add the $anyinit cell and the formalff pass
Jannis Harder
2022-08-16
3
-1
/
+194
*
support file locations containing spaces
Miodrag Milanovic
2022-08-08
1
-1
/
+1
*
sim: Fix $anyseq in nested modules
Jannis Harder
2022-07-22
1
-11
/
+21
*
async2sync: turn FFs with const clks into gclk FFs with feedback
Jannis Harder
2022-06-30
1
-0
/
+3
*
fmcombine: Add _gold/_gate suffix to memids
Jannis Harder
2022-06-03
1
-0
/
+3
*
Observe $TMPDIR variable when creating tmp files
Mohamed A. Bamakhrama
2022-05-27
1
-1
/
+1
*
fix crash when no fst input
Miodrag Milanovic
2022-05-04
1
-1
/
+2
*
Start restoring memory state from VCD/FST
Miodrag Milanovic
2022-05-04
1
-2
/
+17
*
AIM file could have gaps in or between inputs and inits
Miodrag Milanovic
2022-05-02
1
-3
/
+6
*
Match $anyseq input if connected to public wire
Miodrag Milanovic
2022-04-22
1
-6
/
+12
*
Treat $anyseq as input from FST
Miodrag Milanovic
2022-04-22
1
-0
/
+21
*
Last sample from input does not represent change
Miodrag Milanovic
2022-04-22
1
-1
/
+2
*
latches are always set to zero
Miodrag Milanovic
2022-04-22
1
-6
/
+1
*
If not multiclock, output only on clock edges
Miodrag Milanovic
2022-04-22
1
-0
/
+18
*
Set init state for all wires from FST and set past
Miodrag Milanovic
2022-04-22
1
-13
/
+12
*
Fix multiclock for btor2 witness
Miodrag Milanovic
2022-04-22
1
-5
/
+9
*
Fix reading aiw from other solvers
Miodrag Milanovic
2022-04-15
1
-2
/
+2
*
Use wrap_async_control_gate if ff is fine
Miodrag Milanovic
2022-04-08
1
-9
/
+11
*
Makefile: properly conditionalize features requiring compression.
Iris Johnson
2022-04-07
1
-0
/
+2
*
past_ad initial value setting
Miodrag Milanovic
2022-04-02
1
-0
/
+3
*
setInitState can be only one altering values
Miodrag Milanovic
2022-04-02
1
-4
/
+6
*
Set past_d value for init state
Miodrag Milanovic
2022-04-02
1
-0
/
+2
*
Set init values for wrapped async control signals
Miodrag Milanovic
2022-04-01
1
-0
/
+2
*
Support memories in aiw and multiclock
Miodrag Milanovic
2022-03-31
1
-16
/
+86
*
Proper SigBit forming in sim
Miodrag Milanovic
2022-03-22
1
-4
/
+4
*
Proper SigBit forming in sim
Miodrag Milanovic
2022-03-22
1
-4
/
+4
*
More verbose warnings
Miodrag Milanovic
2022-03-18
1
-5
/
+7
*
Recognize registers and set initial state for them in tb
Miodrag Milanovic
2022-03-16
1
-6
/
+32
*
Update sim help message.
Miodrag Milanovic
2022-03-16
1
-1
/
+2
*
Added fst2tb pass for generating testbench
Miodrag Milanovic
2022-03-14
1
-0
/
+319
*
Merge pull request #3229 from YosysHQ/micko/sim_date
Miodrag Milanović
2022-03-11
1
-7
/
+20
|
\
|
*
Add date parameter to enable full date/time and version info
Miodrag Milanovic
2022-03-11
1
-7
/
+20
*
|
Add "sim -q" option
Claire Xenia Wolf
2022-03-11
1
-8
/
+19
|
/
*
Small fix in "sim" help message
Claire Xenia Wolf
2022-03-11
1
-1
/
+1
*
FstData already do conversion to VCD
Miodrag Milanovic
2022-03-11
1
-1
/
+2
*
Support cell name in btor witness file
Miodrag Milanovic
2022-03-11
1
-5
/
+14
*
Proper write of memory data
Miodrag Milanovic
2022-03-11
1
-14
/
+13
*
Start work on memory init
Miodrag Milanovic
2022-03-09
1
-9
/
+34
*
Fixes and error check
Miodrag Milanovic
2022-03-09
1
-1
/
+5
*
cleanup
Miodrag Milanovic
2022-03-07
1
-1
/
+2
*
Error checks for aiger witness
Miodrag Milanovic
2022-03-07
1
-0
/
+7
*
btor2 witness co-simulation
Miodrag Milanovic
2022-03-07
1
-8
/
+123
*
Merge pull request #3219 from YosysHQ/micko/quick_vcd
Miodrag Milanović
2022-03-04
1
-0
/
+1
|
\
|
*
VCD reader support by using external tool
Miodrag Milanovic
2022-02-28
1
-0
/
+1
*
|
Add option to ignore X only signals in output
Miodrag Milanovic
2022-03-02
1
-8
/
+32
*
|
Write simulation files after simulation is performed
Miodrag Milanovic
2022-03-02
1
-145
/
+151
*
|
Cleanup
Miodrag Milanovic
2022-03-02
1
-10
/
+7
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