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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-07 16:32:32 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-07 16:32:32 +0100 |
| commit | ede348cdc285f4b4f1c53942d515a7082e53e37a (patch) | |
| tree | db7782b5bcd207d0f60e0713ef268a58b3e7fe2f /passes/sat | |
| parent | 1b1ecd4ab0c3924d1acbaa0ccc22bd1933cb347c (diff) | |
| download | yosys-ede348cdc285f4b4f1c53942d515a7082e53e37a.tar.gz yosys-ede348cdc285f4b4f1c53942d515a7082e53e37a.tar.bz2 yosys-ede348cdc285f4b4f1c53942d515a7082e53e37a.zip | |
cleanup
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/sim.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 9771e83f3..d7f4de507 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -1238,7 +1238,7 @@ struct SimWorker : SimShared curr_cycle = -1; // force detect change if (curr_cycle != prev_cycle) { - log("Simulating cycle %d %d.\n", cycle, cycle % 1); + log("Simulating cycle %d.\n", cycle); set_inports(clock, State::S1); set_inports(clockn, State::S0); update(); @@ -1282,6 +1282,7 @@ struct SimWorker : SimShared break; } } + register_output_step(10*cycle); write_output_files(); } }; |