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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-02 10:33:41 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-02 19:13:15 +0200 |
| commit | b54aecd80a58dc2a7f5069ee03561d64efdba765 (patch) | |
| tree | f044ede9374804a81c1b8fb87abb5329d9c5103b /passes/sat | |
| parent | 8ca9737180b39011fa75c1d8e34be3100b5b7b41 (diff) | |
| download | yosys-b54aecd80a58dc2a7f5069ee03561d64efdba765.tar.gz yosys-b54aecd80a58dc2a7f5069ee03561d64efdba765.tar.bz2 yosys-b54aecd80a58dc2a7f5069ee03561d64efdba765.zip | |
Set past_d value for init state
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/sim.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 65bd5c78e..d74fbcc4e 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -782,6 +782,7 @@ struct SimInstance { for (auto &it : ff_database) { + ff_state_t &ff = it.second; SigSpec qsig = it.second.data.sig_q; if (qsig.is_wire()) { IdString name = qsig.as_wire()->name; @@ -790,6 +791,7 @@ struct SimInstance log_warning("Unable to find wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(name)).c_str()); if (id!=0) { Const fst_val = Const::from_string(shared->fst->valueOf(id)); + ff.past_d = fst_val; set_state(qsig, fst_val); } } |