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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-22 17:20:17 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-22 17:20:17 +0200 |
| commit | bbfdea2f8a200f40f82600b48afddb66e5f0e1d2 (patch) | |
| tree | c9f26f4fc56c5b336ae8d52c8ce15cca9e1431a3 /passes/sat | |
| parent | 4d80bc24c714f700519a2191a8929fe2136e45a3 (diff) | |
| download | yosys-bbfdea2f8a200f40f82600b48afddb66e5f0e1d2.tar.gz yosys-bbfdea2f8a200f40f82600b48afddb66e5f0e1d2.tar.bz2 yosys-bbfdea2f8a200f40f82600b48afddb66e5f0e1d2.zip | |
Match $anyseq input if connected to public wire
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/sim.cc | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 5a36f87ec..5f795e94c 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -809,13 +809,19 @@ struct SimInstance for (auto cell : module->cells()) { if (cell->type.in(ID($anyseq))) { - SigSpec sig_y= cell->getPort(ID::Y); + SigSpec sig_y = sigmap(cell->getPort(ID::Y)); if (sig_y.is_wire()) { - Wire *wire = sig_y.as_wire(); - fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name)); - if (id==0) - log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str()); - inputs[wire] = id; + bool found = false; + for(auto &item : fst_handles) { + if (item.second==0) continue; // Ignore signals not found + if (sig_y == sigmap(item.first)) { + inputs[sig_y.as_wire()] = item.second; + found = true; + break; + } + } + if (!found) + log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(sig_y.as_wire()->name)).c_str()); } } } |