| Commit message (Expand) | Author | Age | Files | Lines |
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| * | sim: For yw cosim, drive parent module's signals for input ports | Jannis Harder | 2023-02-13 | 1 | -1/+25 |
| * | formalff: Fix crash with _NOT_ gates in -hierarchy mode | Jannis Harder | 2023-01-25 | 1 | -1/+1 |
| * | sim/formalff: Clock handling for yw cosim | Jannis Harder | 2023-01-11 | 2 | -21/+246 |
| * | sim: Improvements and fixes for yw cosim | Jannis Harder | 2023-01-11 | 1 | -4/+91 |
| * | sim: New -append option for Yosys witness cosim | Jannis Harder | 2023-01-11 | 1 | -5/+14 |
| * | sim: Add Yosys witness (.yw) cosimulation | Jannis Harder | 2023-01-11 | 1 | -3/+194 |
| * | sim: Only check formal cells during gclk simulation updates | Jannis Harder | 2023-01-11 | 1 | -16/+19 |
| * | sim: Internal API to set $initstate | Jannis Harder | 2023-01-11 | 1 | -0/+11 |
| * | sim: Emit used memory addresses as signals to output traces | Jannis Harder | 2023-01-11 | 1 | -17/+122 |
| * | Merge branch 'master' into claire/eqystuff | Claire Xen | 2023-01-11 | 2 | -28/+28 |
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| | * | Merge pull request #3537 from jix/xprop | Jannis Harder | 2023-01-11 | 3 | -13/+30 |
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| | * | | Deprecate gcc-4.8 | Miodrag Milanovic | 2023-01-11 | 2 | -28/+28 |
| * | | | Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuff | Claire Xenia Wolf | 2023-01-11 | 3 | -3/+10 |
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| | * | | qbfsat support for cvc5, fixes #3608 | Miodrag Milanovic | 2023-01-09 | 2 | -3/+7 |
| | * | | formalff: Proper error messages on async inputs for the -clk2ff mode | Jannis Harder | 2022-12-09 | 1 | -0/+3 |
| * | | | Allow non-unique modules without state in sim writeback-mode | Claire Xenia Wolf | 2022-12-21 | 1 | -4/+5 |
| * | | | Add gold-x handing to miter cross port handling | Claire Xenia Wolf | 2022-12-08 | 1 | -1/+9 |
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| * | | miter: Add -make_cover option to cover each output pair difference | Jannis Harder | 2022-11-30 | 1 | -0/+14 |
| * | | formalff: Fix -ff2anyinit assertion error for fine FFs | Jannis Harder | 2022-11-30 | 1 | -0/+2 |
| * | | sim: Improved global clock handling | Jannis Harder | 2022-11-30 | 1 | -13/+14 |
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| * | sat: Add -set-def-formal option to force defined $any* outputs | Jannis Harder | 2022-11-28 | 1 | -6/+22 |
| * | Rst docs conversion (#3496) | KrystalDelusion | 2022-11-15 | 1 | -1/+1 |
| * | sim: Run a comb-only update step to set past values during FST cosim | Jannis Harder | 2022-11-07 | 1 | -12/+11 |
| * | Add extra time at the end of a sat VCD trace | Claire Xenia Wolf | 2022-11-01 | 1 | -0/+1 |
| * | Add miter -cross option | Claire Xenia Wolf | 2022-10-24 | 1 | -4/+32 |
| * | clk2fflogic: Always correctly handle simultaneously changing signals | Jannis Harder | 2022-10-07 | 1 | -103/+87 |
| * | mutate: warn if less mutations possible than number requested | N. Engelhardt | 2022-10-05 | 1 | -0/+2 |
| * | Fitting help messages to 80 character width | KrystalDelusion | 2022-08-24 | 2 | -24/+28 |
| * | sim: -hdlname option to preserve flattened hierarchy in sim output | Jannis Harder | 2022-08-16 | 1 | -9/+41 |
| * | clk2fflogic: Generate less unused logic when using verific | Jannis Harder | 2022-08-16 | 1 | -1/+4 |
| * | formalff: New -setundef option | Jannis Harder | 2022-08-16 | 1 | -0/+335 |
| * | formalff: Set new replaced_by_gclk attribute on removed dff's clks | Jannis Harder | 2022-08-16 | 1 | -0/+22 |
| * | Add the $anyinit cell and the formalff pass | Jannis Harder | 2022-08-16 | 3 | -1/+194 |
| * | support file locations containing spaces | Miodrag Milanovic | 2022-08-08 | 1 | -1/+1 |
| * | sim: Fix $anyseq in nested modules | Jannis Harder | 2022-07-22 | 1 | -11/+21 |
| * | async2sync: turn FFs with const clks into gclk FFs with feedback | Jannis Harder | 2022-06-30 | 1 | -0/+3 |
| * | fmcombine: Add _gold/_gate suffix to memids | Jannis Harder | 2022-06-03 | 1 | -0/+3 |
| * | Observe $TMPDIR variable when creating tmp files | Mohamed A. Bamakhrama | 2022-05-27 | 1 | -1/+1 |
| * | fix crash when no fst input | Miodrag Milanovic | 2022-05-04 | 1 | -1/+2 |
| * | Start restoring memory state from VCD/FST | Miodrag Milanovic | 2022-05-04 | 1 | -2/+17 |
| * | AIM file could have gaps in or between inputs and inits | Miodrag Milanovic | 2022-05-02 | 1 | -3/+6 |
| * | Match $anyseq input if connected to public wire | Miodrag Milanovic | 2022-04-22 | 1 | -6/+12 |
| * | Treat $anyseq as input from FST | Miodrag Milanovic | 2022-04-22 | 1 | -0/+21 |
| * | Last sample from input does not represent change | Miodrag Milanovic | 2022-04-22 | 1 | -1/+2 |
| * | latches are always set to zero | Miodrag Milanovic | 2022-04-22 | 1 | -6/+1 |
| * | If not multiclock, output only on clock edges | Miodrag Milanovic | 2022-04-22 | 1 | -0/+18 |
| * | Set init state for all wires from FST and set past | Miodrag Milanovic | 2022-04-22 | 1 | -13/+12 |
| * | Fix multiclock for btor2 witness | Miodrag Milanovic | 2022-04-22 | 1 | -5/+9 |
| * | Fix reading aiw from other solvers | Miodrag Milanovic | 2022-04-15 | 1 | -2/+2 |
| * | Use wrap_async_control_gate if ff is fine | Miodrag Milanovic | 2022-04-08 | 1 | -9/+11 |
