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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-16 07:55:57 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-16 07:55:57 +0100 |
| commit | e217e3017af101bfe43d44c2e3afda3d5c2e0832 (patch) | |
| tree | 760fc9137c6033c68ae53b6b8b4ab08ed4ad7621 /passes/sat | |
| parent | 66914b6eb3eba08d70bc847d3351d7d14eeb0ef7 (diff) | |
| download | yosys-e217e3017af101bfe43d44c2e3afda3d5c2e0832.tar.gz yosys-e217e3017af101bfe43d44c2e3afda3d5c2e0832.tar.bz2 yosys-e217e3017af101bfe43d44c2e3afda3d5c2e0832.zip | |
Update sim help message.
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/sim.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index c46c1509a..5e15faec0 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -1811,7 +1811,8 @@ struct SimPass : public Pass { log(" writeback mode: use final simulation state as new init state\n"); log("\n"); log(" -r\n"); - log(" read simulation results file (file formats supported: FST)\n"); + log(" read simulation results file (file formats supported: FST, VCD, AIW and WIT)\n"); + log(" VCD support requires vcd2fst external tool to be present\n"); log("\n"); log(" -map <filename>\n"); log(" read file with port and latch symbols, needed for AIGER witness input\n"); |