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* past_ad initial value settingMiodrag Milanovic2022-04-021-0/+3
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* setInitState can be only one altering valuesMiodrag Milanovic2022-04-021-4/+6
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* Set past_d value for init stateMiodrag Milanovic2022-04-021-0/+2
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* Set init values for wrapped async control signalsMiodrag Milanovic2022-04-011-0/+2
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* Support memories in aiw and multiclockMiodrag Milanovic2022-03-311-16/+86
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* Proper SigBit forming in simMiodrag Milanovic2022-03-221-4/+4
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* Proper SigBit forming in simMiodrag Milanovic2022-03-221-4/+4
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* More verbose warningsMiodrag Milanovic2022-03-181-5/+7
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* Recognize registers and set initial state for them in tbMiodrag Milanovic2022-03-161-6/+32
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* Update sim help message.Miodrag Milanovic2022-03-161-1/+2
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* Added fst2tb pass for generating testbenchMiodrag Milanovic2022-03-141-0/+319
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* Merge pull request #3229 from YosysHQ/micko/sim_dateMiodrag Milanović2022-03-111-7/+20
|\ | | | | Add date parameter to enable full date/time and version info
| * Add date parameter to enable full date/time and version infoMiodrag Milanovic2022-03-111-7/+20
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* | Add "sim -q" optionClaire Xenia Wolf2022-03-111-8/+19
|/ | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Small fix in "sim" help messageClaire Xenia Wolf2022-03-111-1/+1
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* FstData already do conversion to VCDMiodrag Milanovic2022-03-111-1/+2
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* Support cell name in btor witness fileMiodrag Milanovic2022-03-111-5/+14
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* Proper write of memory dataMiodrag Milanovic2022-03-111-14/+13
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* Start work on memory initMiodrag Milanovic2022-03-091-9/+34
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* Fixes and error checkMiodrag Milanovic2022-03-091-1/+5
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* cleanupMiodrag Milanovic2022-03-071-1/+2
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* Error checks for aiger witnessMiodrag Milanovic2022-03-071-0/+7
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* btor2 witness co-simulationMiodrag Milanovic2022-03-071-8/+123
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* Merge pull request #3219 from YosysHQ/micko/quick_vcdMiodrag Milanović2022-03-041-0/+1
|\ | | | | VCD reader support by using external tool
| * VCD reader support by using external toolMiodrag Milanovic2022-02-281-0/+1
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* | Add option to ignore X only signals in outputMiodrag Milanovic2022-03-021-8/+32
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* | Write simulation files after simulation is performedMiodrag Milanovic2022-03-021-145/+151
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* | CleanupMiodrag Milanovic2022-03-021-10/+7
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* | Refactor sim output writersMiodrag Milanovic2022-02-281-213/+257
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* | Quick fixMiodrag Milanovic2022-02-281-0/+2
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* | Add writing of aiw files to "sim" commandClaire Xenia Wolf2022-02-281-1/+87
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | Hotfix in AIGER witness reader state machineClaire Xenia Wolf2022-02-281-0/+1
|/ | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Support extended aiw formatMiodrag Milanovic2022-02-271-23/+44
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* Fix for last clock edge dataMiodrag Milanovic2022-02-251-3/+1
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* Experimental sim changesClaire Xenia Wolf2022-02-251-20/+22
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* Merge pull request #3211 from YosysHQ/micko/witnessClaire Xen2022-02-221-1/+96
|\ | | | | Add support for AIGER witness files in "sim" command
| * Fix cycle 0 in aiger witness co-simulationClaire Xenia Wolf2022-02-181-12/+15
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Added AIGER witness file co simulationMiodrag Milanovic2022-02-181-1/+93
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* | Fix handling of ce_over_srstMiodrag Milanovic2022-02-211-3/+2
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* simplify logic of handling flip-flops and latchesMiodrag Milanovic2022-02-181-118/+42
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* Review cleanupMiodrag Milanovic2022-02-171-6/+5
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* Add support for various ff/latch cells simulationMiodrag Milanovic2022-02-161-60/+204
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* Merge branch 'master' into clk2ff-better-namesClaire Xen2022-02-1114-88/+534
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| * Merge pull request #3185 from YosysHQ/micko/co_simMiodrag Milanović2022-02-071-21/+430
| |\ | | | | | | Add co-simulation in sim pass
| | * Error detection for co-simulationMiodrag Milanovic2022-02-041-0/+3
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| | * bug fix and cleanupsMiodrag Milanovic2022-02-041-5/+5
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| | * respect hide_internal flagMiodrag Milanovic2022-02-021-1/+1
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| | * unify cycles counting and cleanupMiodrag Milanovic2022-02-021-36/+35
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| | * added stimulus mode and param checkMiodrag Milanovic2022-02-021-5/+31
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| | * error when no signal foundMiodrag Milanovic2022-01-311-0/+2
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