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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-02-25 16:15:32 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-02-25 16:15:32 +0100 |
| commit | fca168797e86b6e501bf3b571380a9daf09d728b (patch) | |
| tree | 23b5ad49889c5166a1cb220c542af1301e993c74 /passes/sat | |
| parent | ca261d3c282f251d816f90dc56db5f5c0b3e308d (diff) | |
| download | yosys-fca168797e86b6e501bf3b571380a9daf09d728b.tar.gz yosys-fca168797e86b6e501bf3b571380a9daf09d728b.tar.bz2 yosys-fca168797e86b6e501bf3b571380a9daf09d728b.zip | |
Fix for last clock edge data
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/sim.cc | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index a5494a088..f28fd21e5 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -1125,7 +1125,7 @@ struct SimWorker : SimShared try { fst->reconstructAllAtTimes(fst_clock, startCount, stopCount, [&](uint64_t time) { log("Co-simulating %s %d [%lu%s].\n", (all_samples ? "sample" : "cycle"), cycle, (unsigned long)time, fst->getTimescaleString()); - bool did_something = time < stopCount; // FIXME + bool did_something = false; for(auto &item : inputs) { std::string v = fst->valueOf(item.second); did_something |= top->set_state(item.first, Const::from_string(v)); @@ -1138,8 +1138,6 @@ struct SimWorker : SimShared } if (did_something) update(); - else - log("nothing to update.\n"); write_output_step(time); bool status = top->checkSignals(); |