diff options
| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-01-31 17:41:50 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-01-31 17:41:50 +0100 |
| commit | 8ba2000a50dcfedbcda57cfebabbfb39caabcfb9 (patch) | |
| tree | 048aead880e439b81dedffeec6c60d1488e51c86 /passes/sat | |
| parent | 1b5ff92e6240c1a12cb3f28adb1b5d0dda77b6e7 (diff) | |
| download | yosys-8ba2000a50dcfedbcda57cfebabbfb39caabcfb9.tar.gz yosys-8ba2000a50dcfedbcda57cfebabbfb39caabcfb9.tar.bz2 yosys-8ba2000a50dcfedbcda57cfebabbfb39caabcfb9.zip | |
error when no signal found
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/sim.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 050fc8d5a..c6fc1518f 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -994,6 +994,8 @@ struct SimWorker : SimShared for (auto wire : topmod->wires()) { if (wire->port_input) { fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name)); + if (id==0) + log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str()); inputs[wire] = id; } } |