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* stoi -> atoiEddie Hung2019-08-071-4/+4
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* Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-061-4/+4
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* Use State::S{0,1}Eddie Hung2019-08-062-6/+6
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* Make liberal use of IdString.in()Eddie Hung2019-08-062-4/+4
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* Error out if enable > dbitsEddie Hung2019-07-131-0/+4
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* memory_dff: Fix checking of feedback mux input when more than one muxDavid Shah2019-07-021-3/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Fix spacingEddie Hung2019-06-251-4/+3
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* Move only one consumer check outside of while loopEddie Hung2019-06-251-6/+5
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* Walk through as many muxes as exist for rd_enEddie Hung2019-06-241-8/+16
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* memory_bram: Fix multiport make_transpDavid Shah2019-04-071-1/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* memory_bram: Consider read enable for address expansion registerDavid Shah2019-04-021-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* memory_bram: Reset make_transp when growing read portsDavid Shah2019-03-271-0/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* memory_bram: Fix multiclock make_transpDavid Shah2019-03-241-9/+16
| | | | Signed-off-by: David Shah <dave@ds0.me>
* memory_collect: do not truncate 'x from \INIT.whitequark2018-12-211-3/+0
| | | | | | | The semantics of an RTLIL constant that has less bits than its declared bit width is zero padding. Therefore, if the output of memory_collect will be used for simulation, truncating 'x from the end of \INIT will produce incorrect simulation results.
* memory_dff: Fix typo when checking init valueDavid Shah2018-12-181-1/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* memory_bram: Fix initdata bit order after shufflingGraham Edgecombe2018-12-111-0/+17
| | | | | | | | | | | | | In some cases the memory_bram pass shuffles the order of the bits in a memory's RD_DATA port. Although the order of the bits in the WR_DATA and WR_EN ports is changed to match the RD_DATA port, the order of the bits in the initialization data is not. This causes reads of initialized memories to return invalid data (until the initialization data is overwritten). This commit fixes the bug by shuffling the initdata bits in exactly the same order as the RD_DATA/WR_DATA/WR_EN bits.
* memory_bram: Reset make_outreg when growing read portsDavid Shah2018-10-191-0/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-209-18/+18
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Disable memory_dff for initialized FFsClifford Wolf2018-05-281-1/+19
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add some cleanup code to memory_nordffClifford Wolf2018-05-281-26/+36
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "memory_nordff" passClifford Wolf2018-03-062-0/+112
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Typo fix.Kaj Tuomi2016-09-081-1/+1
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* Fixed handling of transparent bram rd ports on ROMsClifford Wolf2016-08-271-0/+3
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* Fixed bug in memory_share for memory ports with different ABITSClifford Wolf2016-08-221-0/+6
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* Added memory_memx pass, "memory -memx", and "prep -memx"Clifford Wolf2016-08-193-2/+104
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* Optimize memory address port width in wreduce and memory_collect, not ↵Clifford Wolf2016-08-191-3/+13
| | | | verilog front-end
* Don't sign-extend memory bram initialization dataClifford Wolf2016-05-151-1/+1
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* Added "yosys -D" featureClifford Wolf2016-04-217-7/+7
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* Bugfix and improvements in memory_shareClifford Wolf2016-04-211-22/+19
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* Renamed opt_share to opt_mergeClifford Wolf2016-03-311-1/+1
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* Fixed some visual studio warningsClifford Wolf2016-02-131-1/+1
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* Bugfix in memory_dffClifford Wolf2015-10-311-1/+12
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* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-253-7/+7
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* Bugfix in bram read-enable codeClifford Wolf2015-09-251-2/+5
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* Added read-enable to memory modelClifford Wolf2015-09-255-42/+101
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* Fixed memory_bram for ROMs in BRAMs with write-enable inputsClifford Wolf2015-09-241-1/+1
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* Keep gcc from complaining about uninitialized variablesLarry Doolittle2015-08-141-1/+1
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* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-5/+5
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* Use MEMID as name for $mem cellClifford Wolf2015-08-091-42/+47
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* Added WORDS parameter to $meminitClifford Wolf2015-07-311-7/+25
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* Do not collect disabled $memwr cellsClifford Wolf2015-07-061-15/+18
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* Fixed trailing whitespacesClifford Wolf2015-07-027-21/+21
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* Modernized memory_dff (and fixed a bug)Clifford Wolf2015-06-142-151/+166
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* Added "memory -nordff"Clifford Wolf2015-06-141-2/+9
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* Merge clock inverters in memory_dffClifford Wolf2015-06-091-16/+37
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* Fixed memory_unpack for initialized memoriesClifford Wolf2015-04-291-0/+17
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* Fixed memory_share for unconditional write with part select to memoryClifford Wolf2015-04-221-0/+3
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* Added memory_bram "make_outreg" featureClifford Wolf2015-04-091-2/+25
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* Added support for "file names with blanks"Clifford Wolf2015-04-081-3/+1
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* Added support for initialized bramsClifford Wolf2015-04-061-8/+35
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