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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-25 08:29:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-25 08:29:55 -0700 |
| commit | c4e4902098153a4ab90d383ffc00987fc06ff072 (patch) | |
| tree | a06b01fab85fc7393726017c1045c1d86e2a4225 /passes/memory | |
| parent | b7deaceadde865fa8bca47cfeeb43a82dc936076 (diff) | |
| download | yosys-c4e4902098153a4ab90d383ffc00987fc06ff072.tar.gz yosys-c4e4902098153a4ab90d383ffc00987fc06ff072.tar.bz2 yosys-c4e4902098153a4ab90d383ffc00987fc06ff072.zip | |
Move only one consumer check outside of while loop
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/memory_dff.cc | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index d37cac28e..91ae38fa3 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -189,16 +189,15 @@ struct MemoryDffWorker bool enable_invert = mux_cells_a.count(sig_data) != 0; Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data); check_q = sigmap(mux->getPort(enable_invert ? "\\B" : "\\A")); - sig_data = sigmap(mux->getPort("\\Y")); - for (auto bit : sig_data) - if (sigbit_users_count[bit] > 1) { - goto skip_ff_after_read_merging; - } - en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S")); } while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data)); + for (auto bit : sig_data) + if (sigbit_users_count[bit] > 1) { + goto skip_ff_after_read_merging; + } + if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) && sig_data == check_q) { disconnect_dff(sig_data); |