diff options
| author | whitequark <whitequark@whitequark.org> | 2018-12-21 02:01:27 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2018-12-21 02:01:27 +0000 |
| commit | 0c318e7db513bed1844f594ae780f854ed08e18f (patch) | |
| tree | 31804c863f66c2231db22f99855f02487bbeb2fa /passes/memory | |
| parent | 93d44bb9a613b46a80642b8ce71295db18fadbc5 (diff) | |
| download | yosys-0c318e7db513bed1844f594ae780f854ed08e18f.tar.gz yosys-0c318e7db513bed1844f594ae780f854ed08e18f.tar.bz2 yosys-0c318e7db513bed1844f594ae780f854ed08e18f.zip | |
memory_collect: do not truncate 'x from \INIT.
The semantics of an RTLIL constant that has less bits than its
declared bit width is zero padding. Therefore, if the output of
memory_collect will be used for simulation, truncating 'x from
the end of \INIT will produce incorrect simulation results.
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/memory_collect.cc | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 70d98713c..369fcc84e 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -184,9 +184,6 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) mem->parameters["\\OFFSET"] = Const(memory->start_offset); mem->parameters["\\SIZE"] = Const(memory->size); mem->parameters["\\ABITS"] = Const(addr_bits); - - while (GetSize(init_data) > 1 && init_data.bits.back() == State::Sx && init_data.bits[GetSize(init_data)-2] == State::Sx) - init_data.bits.pop_back(); mem->parameters["\\INIT"] = init_data; log_assert(sig_wr_clk.size() == wr_ports); |