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| author | Clifford Wolf <clifford@clifford.at> | 2015-07-06 13:28:00 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-07-06 13:28:00 +0200 |
| commit | d2ff5d9994f83125578902587bdebd5b749c1beb (patch) | |
| tree | 643ed516d7de4d0b13de59abc7367ca55549a63e /passes/memory | |
| parent | c4dde71dcaffa2b1414817cd4ff4885c12d1defd (diff) | |
| download | yosys-d2ff5d9994f83125578902587bdebd5b749c1beb.tar.gz yosys-d2ff5d9994f83125578902587bdebd5b749c1beb.tar.bz2 yosys-d2ff5d9994f83125578902587bdebd5b749c1beb.zip | |
Do not collect disabled $memwr cells
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/memory_collect.cc | 33 |
1 files changed, 18 insertions, 15 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 6bc4b44ca..134b5e8e1 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -110,21 +110,24 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) SigSpec data = sigmap(cell->getPort("\\DATA")); SigSpec en = sigmap(cell->getPort("\\EN")); - clk.extend_u0(1, false); - clk_enable.extend_u0(1, false); - clk_polarity.extend_u0(1, false); - addr.extend_u0(addr_bits, false); - data.extend_u0(memory->width, false); - en.extend_u0(memory->width, false); - - sig_wr_clk.append(clk); - sig_wr_clk_enable.append(clk_enable); - sig_wr_clk_polarity.append(clk_polarity); - sig_wr_addr.append(addr); - sig_wr_data.append(data); - sig_wr_en.append(en); - - wr_ports++; + if (!en.is_fully_zero()) + { + clk.extend_u0(1, false); + clk_enable.extend_u0(1, false); + clk_polarity.extend_u0(1, false); + addr.extend_u0(addr_bits, false); + data.extend_u0(memory->width, false); + en.extend_u0(memory->width, false); + + sig_wr_clk.append(clk); + sig_wr_clk_enable.append(clk_enable); + sig_wr_clk_polarity.append(clk_polarity); + sig_wr_addr.append(addr); + sig_wr_data.append(data); + sig_wr_en.append(en); + + wr_ports++; + } continue; } |