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| author | Clifford Wolf <clifford@clifford.at> | 2016-08-27 17:06:22 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-08-27 17:06:22 +0200 |
| commit | 23afeadb5e01a7b816c6ae203746caa8ae2aaed7 (patch) | |
| tree | 8565f122de79f622a968ce13d9924499d50caca9 /passes/memory | |
| parent | adcda6817e0df097bf70f8c200edcf15341f3188 (diff) | |
| download | yosys-23afeadb5e01a7b816c6ae203746caa8ae2aaed7.tar.gz yosys-23afeadb5e01a7b816c6ae203746caa8ae2aaed7.tar.bz2 yosys-23afeadb5e01a7b816c6ae203746caa8ae2aaed7.zip | |
Fixed handling of transparent bram rd ports on ROMs
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/memory_bram.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 7b5dd08ab..a7f9cf382 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -656,6 +656,9 @@ grow_read_ports:; bool transp = rd_transp[cell_port_i] == State::S1; SigBit clksig = rd_clk[cell_port_i]; + if (wr_ports == 0) + transp = false; + pair<SigBit, bool> clkdom(clksig, clkpol); if (!clken) clkdom = pair<SigBit, bool>(State::S1, false); |