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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-13 03:39:23 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-13 03:39:23 -0700 |
| commit | ab3917d0791874bab845ca74203c5aaa2ec842d2 (patch) | |
| tree | 2ad7c104f5dd890a3e7cbc1e383cc048bfcafd5f /passes/memory | |
| parent | 463f7100665b38ca346f3919a65ff7626c24c91c (diff) | |
| download | yosys-ab3917d0791874bab845ca74203c5aaa2ec842d2.tar.gz yosys-ab3917d0791874bab845ca74203c5aaa2ec842d2.tar.bz2 yosys-ab3917d0791874bab845ca74203c5aaa2ec842d2.zip | |
Error out if enable > dbits
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/memory_bram.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index ddc56d9b5..aa8f94149 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -68,6 +68,10 @@ struct rules_t if (groups != GetSize(transp)) log_error("Bram %s variant %d has %d groups but only %d entries in 'transp'.\n", log_id(name), variant, groups, GetSize(transp)); if (groups != GetSize(clocks)) log_error("Bram %s variant %d has %d groups but only %d entries in 'clocks'.\n", log_id(name), variant, groups, GetSize(clocks)); if (groups != GetSize(clkpol)) log_error("Bram %s variant %d has %d groups but only %d entries in 'clkpol'.\n", log_id(name), variant, groups, GetSize(clkpol)); + + int group = 0; + for (auto e : enable) + if (e > dbits) log_error("Bram %s variant %d group %d has %d enable bits but only %d dbits.\n", log_id(name), variant, group, e, dbits); } vector<portinfo_t> make_portinfos() const |