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| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2015-08-14 13:22:17 -0700 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-08-14 23:26:49 +0200 |
| commit | 022f570563d8b067e9638bc91bbd168f4c5cb817 (patch) | |
| tree | 66029502692ff5a3043f6099297c55aeff0a1f15 /passes/memory | |
| parent | 03500748192dc93583c0e0f95640865603650714 (diff) | |
| download | yosys-022f570563d8b067e9638bc91bbd168f4c5cb817.tar.gz yosys-022f570563d8b067e9638bc91bbd168f4c5cb817.tar.bz2 yosys-022f570563d8b067e9638bc91bbd168f4c5cb817.zip | |
Keep gcc from complaining about uninitialized variables
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/memory_unpack.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 07ec4564c..a497362bf 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -79,7 +79,7 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) Const initval = memory->parameters.at("\\INIT"); RTLIL::Cell *last_init_cell = nullptr; SigSpec last_init_data; - int last_init_addr; + int last_init_addr=0; for (int i = 0; i < GetSize(initval) && i/mem->width < (1 << abits); i += mem->width) { Const val = initval.extract(i, mem->width, State::Sx); |