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* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Optimize memory address port width in wreduce and memory_collect, not verilog...Clifford Wolf2016-08-191-3/+13
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-1/+1
* Added read-enable to memory modelClifford Wolf2015-09-251-15/+22
* Use MEMID as name for $mem cellClifford Wolf2015-08-091-42/+47
* Do not collect disabled $memwr cellsClifford Wolf2015-07-061-15/+18
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Avoid parameter values with size 0 ($mem cells)Clifford Wolf2015-04-051-5/+5
* Various fixes for memories with offsetsClifford Wolf2015-02-141-3/+8
* Added $meminit support to "memory" commandClifford Wolf2015-02-141-28/+55
* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-241-12/+12
* namespace YosysClifford Wolf2014-09-271-2/+6
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-021-1/+1
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-4/+4
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-14/+14
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-1/+1
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-12/+11
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-14/+14
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-14/+14
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-12/+6
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-241-5/+5
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-7/+0
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-16/+16
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-16/+16
* Changes to "memory" pass for new $memwr/$mem WR_EN interfaceClifford Wolf2014-07-161-2/+2
* Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collectClifford Wolf2014-02-081-0/+1
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-031-2/+7
* Added correct handling of $memwr priorityClifford Wolf2014-01-031-2/+19
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-041-2/+2
* Added help messages to memory_* passesClifford Wolf2013-03-011-7/+23
* initial importClifford Wolf2013-01-051-0/+182