diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-08-02 13:11:01 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-02 13:19:57 +0200 |
| commit | b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3 (patch) | |
| tree | fa56668843c23b8d03a0652be802410f888c6384 /passes/memory/memory_collect.cc | |
| parent | 14412e6c957a34381c33740426b35f7b90a446be (diff) | |
| download | yosys-b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3.tar.gz yosys-b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3.tar.bz2 yosys-b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3.zip | |
More cleanups related to RTLIL::IdString usage
Diffstat (limited to 'passes/memory/memory_collect.cc')
| -rw-r--r-- | passes/memory/memory_collect.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 8887d1952..471a7d53a 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -62,7 +62,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; - if ((cell->type == "$memwr" || cell->type == "$memrd") && cell->parameters["\\MEMID"].decode_string() == memory->name) + if ((cell->type == "$memwr" || cell->type == "$memrd") && memory->name == cell->parameters["\\MEMID"].decode_string()) memcells.push_back(cell); } @@ -70,7 +70,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) for (auto cell : memcells) { - if (cell->type == "$memwr" && cell->parameters["\\MEMID"].decode_string() == memory->name) + if (cell->type == "$memwr" && memory->name == cell->parameters["\\MEMID"].decode_string()) { wr_ports++; del_cells.push_back(cell); @@ -97,7 +97,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) sig_wr_en.append(en); } - if (cell->type == "$memrd" && cell->parameters["\\MEMID"].decode_string() == memory->name) + if (cell->type == "$memrd" && memory->name == cell->parameters["\\MEMID"].decode_string()) { rd_ports++; del_cells.push_back(cell); @@ -129,7 +129,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) sstr << "$mem$" << memory->name << "$" << (autoidx++); RTLIL::Cell *mem = module->addCell(sstr.str(), "$mem"); - mem->parameters["\\MEMID"] = RTLIL::Const(memory->name); + mem->parameters["\\MEMID"] = RTLIL::Const(memory->name.str()); mem->parameters["\\WIDTH"] = RTLIL::Const(memory->width); mem->parameters["\\OFFSET"] = RTLIL::Const(memory->start_offset); mem->parameters["\\SIZE"] = RTLIL::Const(memory->size); |