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author | Clifford Wolf <clifford@clifford.at> | 2015-02-14 14:21:15 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-02-14 14:21:15 +0100 |
commit | e9368a1d7e13bc691f86f25cd80981110b937cab (patch) | |
tree | b3dd1332d669c288d45c52595607ff6b2f364a48 /passes/memory/memory_collect.cc | |
parent | dcf2e242406d563254013ea7db4b29b55be96eff (diff) | |
download | yosys-e9368a1d7e13bc691f86f25cd80981110b937cab.tar.gz yosys-e9368a1d7e13bc691f86f25cd80981110b937cab.tar.bz2 yosys-e9368a1d7e13bc691f86f25cd80981110b937cab.zip |
Various fixes for memories with offsets
Diffstat (limited to 'passes/memory/memory_collect.cc')
-rw-r--r-- | passes/memory/memory_collect.cc | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index d0d32f504..96d0ada03 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -38,8 +38,6 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) memory->name.c_str(), module->name.c_str()); int addr_bits = 0; - while ((1 << addr_bits) < memory->size) - addr_bits++; Const init_data(State::Sx, memory->size * memory->width); SigMap sigmap(module); @@ -64,8 +62,15 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; - if (cell->type.in("$memrd", "$memwr", "$meminit") && memory->name == cell->parameters["\\MEMID"].decode_string()) + if (cell->type.in("$memrd", "$memwr", "$meminit") && memory->name == cell->parameters["\\MEMID"].decode_string()) { + addr_bits = std::max(addr_bits, cell->getParam("\\ABITS").as_int()); memcells.push_back(cell); + } + } + + if (memcells.empty()) { + log(" no cells found. removing memory.\n"); + return; } std::sort(memcells.begin(), memcells.end(), memcells_cmp); |