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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:51:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:51:45 +0200 |
| commit | 4c4b6021562c598c4510831bd547edaa97d14dac (patch) | |
| tree | 7d8bde9d617e67431bdb6c51b5e27ea1836fe7a5 /passes/memory/memory_collect.cc | |
| parent | f9946232adf887e5aa4a48c64f88eaa17e424009 (diff) | |
| download | yosys-4c4b6021562c598c4510831bd547edaa97d14dac.tar.gz yosys-4c4b6021562c598c4510831bd547edaa97d14dac.tar.bz2 yosys-4c4b6021562c598c4510831bd547edaa97d14dac.zip | |
Refactoring: Renamed RTLIL::Module::cells to cells_
Diffstat (limited to 'passes/memory/memory_collect.cc')
| -rw-r--r-- | passes/memory/memory_collect.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index a8caf883f..d5995ee0e 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -61,7 +61,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) std::vector<RTLIL::Cell*> del_cells; std::vector<RTLIL::Cell*> memcells; - for (auto &cell_it : module->cells) { + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; if ((cell->type == "$memwr" || cell->type == "$memrd") && cell->parameters["\\MEMID"].decode_string() == memory->name) memcells.push_back(cell); |