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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-31 13:19:47 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-31 13:19:47 +0200 |
| commit | 1cb25c05b37b0172dbc50e140fe20f25d973dd8a (patch) | |
| tree | 4bccb9f45ccad05346697c79afca9a1b21dced9c /passes/memory/memory_collect.cc | |
| parent | 1202f7aa4bb0f9afde157ebc4701d64e7e38abd8 (diff) | |
| download | yosys-1cb25c05b37b0172dbc50e140fe20f25d973dd8a.tar.gz yosys-1cb25c05b37b0172dbc50e140fe20f25d973dd8a.tar.bz2 yosys-1cb25c05b37b0172dbc50e140fe20f25d973dd8a.zip | |
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Diffstat (limited to 'passes/memory/memory_collect.cc')
| -rw-r--r-- | passes/memory/memory_collect.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 40c68abc1..aecb7bd6c 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -126,7 +126,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) } std::stringstream sstr; - sstr << "$mem$" << memory->name << "$" << (RTLIL::autoidx++); + sstr << "$mem$" << memory->name << "$" << (autoidx++); RTLIL::Cell *mem = module->addCell(sstr.str(), "$mem"); mem->parameters["\\MEMID"] = RTLIL::Const(memory->name); |