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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-03 13:01:45 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-03 13:01:45 +0100 |
| commit | a6750b375301f2c2ebb51a2496cdf2c820b2546b (patch) | |
| tree | e3a91710abab3a7a89858426b0d17601946d8fec /passes/memory/memory_collect.cc | |
| parent | de9226a64f96a3731008218727d6b3897c58f593 (diff) | |
| download | yosys-a6750b375301f2c2ebb51a2496cdf2c820b2546b.tar.gz yosys-a6750b375301f2c2ebb51a2496cdf2c820b2546b.tar.bz2 yosys-a6750b375301f2c2ebb51a2496cdf2c820b2546b.zip | |
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Diffstat (limited to 'passes/memory/memory_collect.cc')
| -rw-r--r-- | passes/memory/memory_collect.cc | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index ad4df228e..40504d781 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -54,6 +54,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) RTLIL::SigSpec sig_rd_clk; RTLIL::SigSpec sig_rd_clk_enable; RTLIL::SigSpec sig_rd_clk_polarity; + RTLIL::SigSpec sig_rd_transparent; RTLIL::SigSpec sig_rd_addr; RTLIL::SigSpec sig_rd_data; @@ -105,18 +106,21 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) RTLIL::SigSpec clk = cell->connections["\\CLK"]; RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]); RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]); + RTLIL::SigSpec transparent = RTLIL::SigSpec(cell->parameters["\\TRANSPARENT"]); RTLIL::SigSpec addr = cell->connections["\\ADDR"]; RTLIL::SigSpec data = cell->connections["\\DATA"]; clk.extend(1, false); clk_enable.extend(1, false); clk_polarity.extend(1, false); + transparent.extend(1, false); addr.extend(addr_bits, false); data.extend(memory->width, false); sig_rd_clk.append(clk); sig_rd_clk_enable.append(clk_enable); sig_rd_clk_polarity.append(clk_polarity); + sig_rd_transparent.append(transparent); sig_rd_addr.append(addr); sig_rd_data.append(data); } @@ -147,7 +151,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports); mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.chunks[0].data : RTLIL::Const(0, 0); - mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_enable.chunks[0].data : RTLIL::Const(0, 0); + mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.chunks[0].data : RTLIL::Const(0, 0); mem->connections["\\WR_CLK"] = sig_wr_clk; mem->connections["\\WR_ADDR"] = sig_wr_addr; @@ -165,7 +169,8 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports); mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.chunks[0].data : RTLIL::Const(0, 0); - mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_enable.chunks[0].data : RTLIL::Const(0, 0); + mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.chunks[0].data : RTLIL::Const(0, 0); + mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.chunks[0].data : RTLIL::Const(0, 0); mem->connections["\\RD_CLK"] = sig_rd_clk; mem->connections["\\RD_ADDR"] = sig_rd_addr; |