iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	memory_collect: Copy attr from RTLIL::Memory to cell	David Shah	2019-11-18	1	-0/+4
*	Use State::S{0,1}	Eddie Hung	2019-08-06	1	-5/+5
*	memory_collect: do not truncate 'x from \INIT.	whitequark	2018-12-21	1	-3/+0
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Optimize memory address port width in wreduce and memory_collect, not verilog...	Clifford Wolf	2016-08-19	1	-3/+13
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25	1	-1/+1
*	Added read-enable to memory model	Clifford Wolf	2015-09-25	1	-15/+22
*	Use MEMID as name for $mem cell	Clifford Wolf	2015-08-09	1	-42/+47
*	Do not collect disabled $memwr cells	Clifford Wolf	2015-07-06	1	-15/+18
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	Avoid parameter values with size 0 ($mem cells)	Clifford Wolf	2015-04-05	1	-5/+5
*	Various fixes for memories with offsets	Clifford Wolf	2015-02-14	1	-3/+8
*	Added $meminit support to "memory" command	Clifford Wolf	2015-02-14	1	-28/+55
*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24	1	-12/+12
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-2/+6
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-1/+1
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-4/+4
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-14/+14
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-1/+1
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-12/+11
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-14/+14
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-14/+14
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-12/+6
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-5/+5
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-7/+0
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-16/+16
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-16/+16
*	Changes to "memory" pass for new $memwr/$mem WR_EN interface	Clifford Wolf	2014-07-16	1	-2/+2
*	Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect	Clifford Wolf	2014-02-08	1	-0/+1
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-2/+7
*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03	1	-2/+19
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	1	-2/+2
*	Added help messages to memory_* passes	Clifford Wolf	2013-03-01	1	-7/+23
*	initial import	Clifford Wolf	2013-01-05	1	-0/+182