iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Some improvements in FSM mapping and recoding	Clifford Wolf	2014-08-14	1	-1/+1
*	Fixed FSM mapping for multiple reset-like signals	Clifford Wolf	2014-08-10	1	-1/+21
*	Some improvements in fsm_opt and fsm_map for FSM with unreachable states	Clifford Wolf	2014-08-09	1	-50/+57
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-24/+24
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-15/+5
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-28/+28
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-28/+28
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-52/+16
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-5/+0
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-8/+8
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-8/+8
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-15/+15
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-15/+15
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	1	-1/+1
*	Improved FSM one-hot encoding, added binary encoding	Clifford Wolf	2013-05-24	1	-24/+32
*	Added help messages for fsm_* passes	Clifford Wolf	2013-03-01	1	-3/+14
*	initial import	Clifford Wolf	2013-01-05	1	-0/+356