diff options
author | Clifford Wolf <clifford@clifford.at> | 2013-03-01 12:35:12 +0100 |
---|---|---|
committer | Clifford Wolf <clifford@clifford.at> | 2013-03-01 12:35:12 +0100 |
commit | a338d1a082726d84210912318a9ac49977dc380c (patch) | |
tree | e025f50cbc314b882c911aaa4083f91608836cac /passes/fsm/fsm_map.cc | |
parent | f3a849512f2c7def98fcfa56de74d8a6bdc8b8fc (diff) | |
download | yosys-a338d1a082726d84210912318a9ac49977dc380c.tar.gz yosys-a338d1a082726d84210912318a9ac49977dc380c.tar.bz2 yosys-a338d1a082726d84210912318a9ac49977dc380c.zip |
Added help messages for fsm_* passes
Diffstat (limited to 'passes/fsm/fsm_map.cc')
-rw-r--r-- | passes/fsm/fsm_map.cc | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 4319dc044..063af587d 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -337,16 +337,27 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) } struct FsmMapPass : public Pass { - FsmMapPass() : Pass("fsm_map") { } + FsmMapPass() : Pass("fsm_map", "mapping FSMs to basic logic") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" fsm_map [selection]\n"); + log("\n"); + log("This pass translates FSM cells to flip-flops and logic.\n"); + log("\n"); + } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { - log_header("Executing FSM_MAP pass (simple optimizations of FSMs).\n"); + log_header("Executing FSM_MAP pass (mapping FSMs to basic logic).\n"); extra_args(args, 1, design); for (auto &mod_it : design->modules) { + if (!design->selected(mod_it.second)) + continue; std::vector<RTLIL::Cell*> fsm_cells; for (auto &cell_it : mod_it.second->cells) - if (cell_it.second->type == "$fsm") + if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) fsm_cells.push_back(cell_it.second); for (auto cell : fsm_cells) map_fsm(cell, mod_it.second); |