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author | Clifford Wolf <clifford@clifford.at> | 2014-08-14 11:22:45 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-08-14 11:22:45 +0200 |
commit | 28cf48e31f049f8343023de46cd916ac47fcfc5d (patch) | |
tree | a9f23f5705ab78e95a5f03cd55430942beae6862 /passes/fsm/fsm_map.cc | |
parent | 996c06f64dcb1619584c88d101c5ba258b2b26af (diff) | |
download | yosys-28cf48e31f049f8343023de46cd916ac47fcfc5d.tar.gz yosys-28cf48e31f049f8343023de46cd916ac47fcfc5d.tar.bz2 yosys-28cf48e31f049f8343023de46cd916ac47fcfc5d.zip |
Some improvements in FSM mapping and recoding
Diffstat (limited to 'passes/fsm/fsm_map.cc')
-rw-r--r-- | passes/fsm/fsm_map.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 048cf7e5f..60580eb46 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -285,7 +285,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) } } - RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$safe_pmux"); + RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$pmux"); mux_cell->setPort("\\A", sig_a); mux_cell->setPort("\\B", sig_b); mux_cell->setPort("\\S", sig_s); |