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author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 10:18:00 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 11:18:30 +0200 |
commit | 10e5791c5e5660cb784503d36439ee90d61eb06b (patch) | |
tree | d7bd3d8f1d0254e14fcf68ce25545f42afab9724 /passes/fsm/fsm_map.cc | |
parent | d088854b47f5f77c6a62be2ba4b895164938d7a2 (diff) | |
download | yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.tar.gz yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.tar.bz2 yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.zip |
Refactoring: Renamed RTLIL::Design::modules to modules_
Diffstat (limited to 'passes/fsm/fsm_map.cc')
-rw-r--r-- | passes/fsm/fsm_map.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index f6ef12a7a..8b9ad6be7 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -309,7 +309,7 @@ struct FsmMapPass : public Pass { log_header("Executing FSM_MAP pass (mapping FSMs to basic logic).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; std::vector<RTLIL::Cell*> fsm_cells; |