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author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:51:45 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:51:45 +0200 |
commit | 4c4b6021562c598c4510831bd547edaa97d14dac (patch) | |
tree | 7d8bde9d617e67431bdb6c51b5e27ea1836fe7a5 /passes/fsm/fsm_map.cc | |
parent | f9946232adf887e5aa4a48c64f88eaa17e424009 (diff) | |
download | yosys-4c4b6021562c598c4510831bd547edaa97d14dac.tar.gz yosys-4c4b6021562c598c4510831bd547edaa97d14dac.tar.bz2 yosys-4c4b6021562c598c4510831bd547edaa97d14dac.zip |
Refactoring: Renamed RTLIL::Module::cells to cells_
Diffstat (limited to 'passes/fsm/fsm_map.cc')
-rw-r--r-- | passes/fsm/fsm_map.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 7ab159540..f6ef12a7a 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -313,7 +313,7 @@ struct FsmMapPass : public Pass { if (!design->selected(mod_it.second)) continue; std::vector<RTLIL::Cell*> fsm_cells; - for (auto &cell_it : mod_it.second->cells) + for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) fsm_cells.push_back(cell_it.second); for (auto cell : fsm_cells) |