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* kernel/rtlil: Extract some helpers for checking memory cell types.Marcelina Kościelnicka2021-05-221-0/+10
| | | | | | There will soon be more (versioned) memory cells, so handle passes that only care if a cell is memory-related by a simple helper call instead of a hardcoded list.
* rtlil: add const accessors for modules, wires, and cellsZachary Snow2021-03-251-0/+5
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* blackbox: Include whiteboxed modulesgatecat2021-03-171-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* rtlil: Disallow 0-width chunks in SigSpec.Marcelina Kościelnicka2021-03-151-18/+49
| | | | | | | | | Among other problems, this also fixes equality comparisons between SigSpec by enforcing a canonical form. Also fix another minor issue with possible non-canonical SigSpec. Fixes #2623.
* Add support for memory writes in processes.Marcelina Kościelnicka2021-03-081-0/+1
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* Replace assert in addModule with more useful error messageDan Ravensloft2021-03-061-1/+2
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* bugpoint: add -wires option.whitequark2020-12-071-1/+1
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* Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-261-2/+2
| | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
* Ensure \A_SIGNED is never used with $shiftxXiretza2020-08-181-1/+5
| | | | | It has no effect on the output ($shiftx doesn't perform any sign extension whatsoever), so an attempt to use it should be caught early.
* Add add* functions for the new FF typesMarcelina Kościelnicka2020-06-231-0/+193
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* Add new builtin FF typesMarcelina Kościelnicka2020-06-231-47/+224
| | | | | | | | | | | | | | The new types include: - FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`) - FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`) - FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`) - FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`) - FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`) - latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`) The new FF types are not actually used anywhere yet (this is left for future commits).
* RTLIL: add Module::addProcess, use it in Module::cloneInto. NFC.whitequark2020-06-091-2/+10
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* flatten: preserve original object names via hdlname attribute.whitequark2020-06-081-0/+16
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* RTLIL: use {get,set}_string_attribute in {get,set}_strpool_attribute.whitequark2020-06-081-2/+2
| | | | | The only difference in behavior is that this removes the attribute when the pool becomes empty.
* Merge pull request #2105 from whitequark/split-flatten-off-techmapclairexen2020-06-081-0/+12
|\ | | | | Split `flatten` from `techmap` and simplify it
| * RTLIL: factor out RTLIL::Module::addMemory. NFC.whitequark2020-06-041-0/+12
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* | Merge pull request #2006 from jersey99/signed-in-rtlil-wirewhitequark2020-06-041-0/+2
|\ \ | |/ |/| Preserve 'signed'-ness of a verilog wire through RTLIL
| * Preserve 'signed'-ness of a verilog wire through RTLILVamsi K Vytla2020-04-271-0/+2
| | | | | | | | | | | | | | | | | | As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now: RTLIL::wire holds an is_signed field. This is exported in JSON backend This is exported via dump_rtlil command This is read in via ilang_parser
* | Add flooring division operatorXiretza2020-05-281-1/+2
| | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
* | Add flooring modulo operatorXiretza2020-05-281-1/+2
|/ | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* kernel: Cell::getParam() to throw exception again if not foundEddie Hung2020-04-221-3/+2
| | | | As it did before #1945
* Use default parameter value in getParamMarcelina Kościelnicka2020-04-211-1/+10
| | | | Fixes #1822.
* ilang, ast: Store parameter order and default value information.Marcelina Kościelnicka2020-04-211-1/+2
| | | | Fixes #1819, #1820.
* rtlil: add AttrObject::has_attribute.whitequark2020-04-161-0/+5
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* rtlil: add AttrObject::{get,set}_string_attribute.whitequark2020-04-161-17/+17
| | | | And make {get,set}_src_attribute use those functions.
* Merge pull request #1927 from YosysHQ/eddie/design_remove_assertEddie Hung2020-04-161-0/+1
|\ | | | | kernel: Design::remove(RTLIL::Module *) to check refcount_modules_
| * kernel: Design::remove(RTLIL::Module *) to check refcount_modules_Eddie Hung2020-04-141-0/+1
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* | kernel: Module::makeblackbox() to clear connections tooEddie Hung2020-04-131-0/+2
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* Merge pull request #1858 from YosysHQ/eddie/fix1856Eddie Hung2020-04-091-1/+1
|\ | | | | kernel: include "kernel/constids.inc"
| * kernel: include "kernel/constids.inc" instead of "constids.inc"Eddie Hung2020-04-091-1/+1
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* | [NFCI] Deduplicate builtin FF cell types listMarcelina Kościelnicka2020-04-091-0/+47
|/ | | | | | | | | A few passes included the same list of FF cell types. Make it a global const instead. The zinit pass also seems to include a list like that, but given that it seems to be completely broken at the time (see #1568 discussion), I'm going to pretend I didn't see that.
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-410/+410
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* kernel: Use constids.inc for global/constant IdStringsEddie Hung2020-04-021-6/+4
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* Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-021-288/+244
|\ | | | | kernel: speedup by using more pass-by-const-ref
| * kernel: pass-by-value into Design::scratchpad_set_string() tooEddie Hung2020-03-271-2/+2
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| * kernel: Cell::set{Port,Param}() to pass by value, but use std::moveEddie Hung2020-03-261-5/+5
| | | | | | | | Otherwise cell->setPort(ID::A, cell->getPort(ID::B)) could be invalid
| * kernel: SigSpec copies to not trigger pack()Eddie Hung2020-03-181-33/+4
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| * kernel: more pass by const ref, more speedupsEddie Hung2020-03-181-180/+174
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| * kernel: speedupEddie Hung2020-03-181-30/+23
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| * kernel: fix DeleteWireWorkerEddie Hung2020-03-171-9/+4
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| * kernel: SigSpec use more const& + overloads to prevent implicit SigSpecEddie Hung2020-03-131-31/+39
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| * kernel: optimise Module::remove(const pool<RTLIL::Wire*>()Eddie Hung2020-03-121-10/+5
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* | Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-271-0/+2
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.
* Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-231-2/+0
| | | | and RTLIL nodes.
* specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-2/+6
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* Add RTLIL::constpad, init by yosys_setup(); use for abc9Eddie Hung2020-01-081-0/+1
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* Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputsClifford Wolf2020-01-021-4/+25
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.whitequark2019-12-041-3/+21
| | | | | | | Before this commit, these cells would accept any \B_SIGNED and in case of \B_SIGNED=1, would still treat the \B input as unsigned. Also fix the Verilog frontend to never emit such constructs.
* Fix for SigSpec() == SigSpec(State::Sx, 0) to be true againEddie Hung2019-10-041-0/+6
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* Fix typoEddie Hung2019-09-301-1/+1
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