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author | Rupert Swarbrick <rswarbrick@lowrisc.org> | 2020-03-17 09:34:31 +0000 |
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committer | Rupert Swarbrick <rswarbrick@gmail.com> | 2020-03-27 16:08:26 +0000 |
commit | 044ca9dde409e3c91542fe95513d6641110f8462 (patch) | |
tree | 564c849ec0a8884171e22d89843e7e9c3e9115b0 /kernel/rtlil.cc | |
parent | 4c38895fab3ca2426ffc23e40601f3042a953e47 (diff) | |
download | yosys-044ca9dde409e3c91542fe95513d6641110f8462.tar.gz yosys-044ca9dde409e3c91542fe95513d6641110f8462.tar.bz2 yosys-044ca9dde409e3c91542fe95513d6641110f8462.zip |
Add support for SystemVerilog-style `define to Verilog frontend
This patch should support things like
`define foo(a, b = 3, c) a+b+c
`foo(1, ,2)
which will evaluate to 1+3+2. It also spots mistakes like
`foo(1)
(the 3rd argument doesn't have a default value, so a call site is
required to set it).
Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.
Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.
Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 06181b763..79e50cccd 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -21,6 +21,7 @@ #include "kernel/macc.h" #include "kernel/celltypes.h" #include "frontends/verilog/verilog_frontend.h" +#include "frontends/verilog/preproc.h" #include "backends/ilang/ilang_backend.h" #include <string.h> @@ -379,6 +380,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) } RTLIL::Design::Design() + : verilog_defines (new define_map_t) { static unsigned int hashidx_count = 123456789; hashidx_count = mkhash_xorshift(hashidx_count); |