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author | Eddie Hung <eddie@fpgeh.com> | 2020-03-26 14:33:06 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-26 14:33:06 -0700 |
commit | f97b90e40b9a9b8e8b8ea692c651464980721ce4 (patch) | |
tree | 5cf78a4af1a31ecb46799c93664c178f69203e6b /kernel/rtlil.cc | |
parent | 940640ac4472a83fb575838e66cceeedcb785b61 (diff) | |
download | yosys-f97b90e40b9a9b8e8b8ea692c651464980721ce4.tar.gz yosys-f97b90e40b9a9b8e8b8ea692c651464980721ce4.tar.bz2 yosys-f97b90e40b9a9b8e8b8ea692c651464980721ce4.zip |
kernel: Cell::set{Port,Param}() to pass by value, but use std::move
Otherwise cell->setPort(ID::A, cell->getPort(ID::B)) could be invalid
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r-- | kernel/rtlil.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 6eb698b2b..baa033401 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2481,11 +2481,11 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname) } } -void RTLIL::Cell::setPort(RTLIL::IdString portname, const RTLIL::SigSpec &signal) +void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal) { auto r = connections_.insert(portname); auto conn_it = r.first; - if (conn_it->second == signal) + if (!r.second && conn_it->second == signal) return; for (auto mon : module->monitors) @@ -2500,7 +2500,7 @@ void RTLIL::Cell::setPort(RTLIL::IdString portname, const RTLIL::SigSpec &signal log_backtrace("-X- ", yosys_xtrace-1); } - conn_it->second = signal; + conn_it->second = std::move(signal); } const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const @@ -2556,9 +2556,9 @@ void RTLIL::Cell::unsetParam(RTLIL::IdString paramname) parameters.erase(paramname); } -void RTLIL::Cell::setParam(RTLIL::IdString paramname, const RTLIL::Const &value) +void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value) { - parameters[paramname] = value; + parameters[paramname] = std::move(value); } const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const |