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* fixed Verilog parser filename and line numbering issue with include filesJohann Glaser2013-08-211-0/+2
* Added support for include directories with the new '-I' argument of theJohann Glaser2013-08-203-4/+24
* Added support for notif0/notif1 primitivesJohann Glaser2013-08-202-4/+8
* Fixed width and sign detection for ** operatorClifford Wolf2013-08-191-3/+3
* Added support for bufif0/bufif1 primitivesClifford Wolf2013-08-192-33/+59
* Improved ast dumping (ast/verilog frontend)Clifford Wolf2013-08-194-64/+35
* Added support for "2**n" shifter encodingClifford Wolf2013-08-121-0/+4
* Added $div and $mod technology mappingClifford Wolf2013-08-091-1/+1
* Added "design" command (-reset, -save, -load)Clifford Wolf2013-07-272-0/+16
* More fixes in ternary op sign handlingClifford Wolf2013-07-121-0/+3
* Fixed sign handling in ternary operatorClifford Wolf2013-07-121-2/+2
* Another vloghammer related bugfixClifford Wolf2013-07-111-1/+1
* Fixed sign propagation in bit-wise operatorsClifford Wolf2013-07-091-0/+1
* More fixes in ast expression sign/width handlingClifford Wolf2013-07-091-9/+8
* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-093-35/+169
* Fixed another bug found using vloghammerClifford Wolf2013-07-071-1/+1
* Fixed AST_CONSTANT node generationClifford Wolf2013-07-071-1/+1
* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-046-13/+63
* More fixes for bugs found using xsthammerClifford Wolf2013-06-133-8/+16
* Further improved and extended xsthammerClifford Wolf2013-06-111-0/+1
* Sign-extension related fixes in SatGen and AST frontendClifford Wolf2013-06-101-0/+2
* Fixes and improvements in AST const foldingClifford Wolf2013-06-102-1/+11
* Enabled AST/Verilog front-end optimizations per defaultClifford Wolf2013-06-105-11/+30
* Added SAT generator and simple sat_solve commandClifford Wolf2013-06-072-3/+4
* Added log_assert() apiClifford Wolf2013-05-241-2/+1
* Fixed memory leak in ilang frontendClifford Wolf2013-05-231-0/+1
* added option '-Dname[=definition]' to command 'read_verilog'Johann Glaser2013-05-193-4/+19
* Merge branch 'bugfix'Clifford Wolf2013-05-161-2/+0
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| * Fixed synthesis of functions in latched blocksClifford Wolf2013-05-161-2/+0
* | Added support for verilog === operatorClifford Wolf2013-05-071-0/+2
* | Fixed handling of positional module parametersClifford Wolf2013-04-261-6/+4
* | Only use sha1 checksums for names of parametric modules when the verbose form...Clifford Wolf2013-04-261-9/+20
* | Fixed a bug in AST frontend for cases with non-blocking assigned variables as...Clifford Wolf2013-04-131-4/+4
* | Now only use value from "initial" when no matching "always" block is foundClifford Wolf2013-03-313-7/+31
* | Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)Clifford Wolf2013-03-315-3/+15
* | Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-283-6/+30
* | Improvements and bugfixes for generate blocks with local signalsClifford Wolf2013-03-262-4/+2
* | Fixed handling of unconditional generate blocksClifford Wolf2013-03-262-1/+19
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* Added nosync attribute and some async reset related fixesClifford Wolf2013-03-253-34/+16
* Added mem2reg option to verilog frontendClifford Wolf2013-03-244-11/+28
* Another fix in mem2reg ast simplify logicClifford Wolf2013-03-241-1/+3
* Improved mem2reg handling in ast simplifierClifford Wolf2013-03-242-5/+35
* Tiny fixes to verilog parserClifford Wolf2013-03-232-1/+9
* Added help messages to ilang and verilog frontendsClifford Wolf2013-03-012-2/+57
* Moved stand-alone libs to libs/ directory and added libs/subcircuitClifford Wolf2013-02-274-4/+4
* Added support for verilog genblock[index].member syntaxClifford Wolf2013-02-264-11/+33
* Added support for "always @(*)"Clifford Wolf2013-01-161-0/+3
* added .gitignore filesClifford Wolf2013-01-052-0/+8
* initial importClifford Wolf2013-01-0517-0/+5999
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