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| author | Clifford Wolf <clifford@clifford.at> | 2013-08-09 17:09:24 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-08-09 17:09:24 +0200 |
| commit | c8763301b436d05c1040adb1615e75ccbfde93e8 (patch) | |
| tree | 2ff9f7d45c98f567cd86be154cba405549f1903c /frontends | |
| parent | 376150c9265e01a7b012d716db0325af3776b6b0 (diff) | |
| download | yosys-c8763301b436d05c1040adb1615e75ccbfde93e8.tar.gz yosys-c8763301b436d05c1040adb1615e75ccbfde93e8.tar.bz2 yosys-c8763301b436d05c1040adb1615e75ccbfde93e8.zip | |
Added $div and $mod technology mapping
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index e7ceec5f9..9c027878a 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -968,7 +968,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (width > width_hint && width_hint > 0) width = width_hint; if (width < width_hint) { - if (type == AST_ADD || type == AST_SUB) + if (type == AST_ADD || type == AST_SUB || type == AST_DIV) width++; if (type == AST_SUB && (!children[0]->is_signed || !children[1]->is_signed)) width = width_hint; |