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| author | Clifford Wolf <clifford@clifford.at> | 2013-07-12 13:13:04 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-07-12 13:13:04 +0200 |
| commit | 3650fd7fbe45a00792770d9ecb9397bc27ea0845 (patch) | |
| tree | 0ecf122082e664a9d2d7267bca5a17e8852fba62 /frontends | |
| parent | ded769c98cffe5682c0211dba08abc4a1efe3d5a (diff) | |
| download | yosys-3650fd7fbe45a00792770d9ecb9397bc27ea0845.tar.gz yosys-3650fd7fbe45a00792770d9ecb9397bc27ea0845.tar.bz2 yosys-3650fd7fbe45a00792770d9ecb9397bc27ea0845.zip | |
More fixes in ternary op sign handling
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index a9574254d..e7ceec5f9 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -998,6 +998,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // generate multiplexer for ternary operator (aka ?:-operator) case AST_TERNARY: { + if (width_hint < 0) + detectSignWidth(width_hint, sign_hint); + RTLIL::SigSpec cond = children[0]->genRTLIL(); RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint); RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint); |