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| author | Clifford Wolf <clifford@clifford.at> | 2013-08-12 14:47:50 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-08-12 14:47:50 +0200 |
| commit | 759852914df00609f8797315c6cec76f1c8a3981 (patch) | |
| tree | bac67cdfc87d57a7f3e12e41aad71424d0d29ea9 /frontends | |
| parent | ccf36cb7d81a9513db15b8a36c240d2c7ec9f5b5 (diff) | |
| download | yosys-759852914df00609f8797315c6cec76f1c8a3981.tar.gz yosys-759852914df00609f8797315c6cec76f1c8a3981.tar.bz2 yosys-759852914df00609f8797315c6cec76f1c8a3981.zip | |
Added support for "2**n" shifter encoding
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 9c027878a..50e959754 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -974,8 +974,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) width = width_hint; if (type == AST_MUL) width = std::min(left.width + right.width, width_hint); + if (type == AST_POW) + width = width_hint; } is_signed = children[0]->is_signed && children[1]->is_signed; + if (!flag_noopt && type == AST_POW && left.is_fully_const() && left.as_int() == 2) + return binop2rtlil(this, "$shl", width, RTLIL::SigSpec(1, left.width), right); return binop2rtlil(this, type_name, width, left, right); } |