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author | Clifford Wolf <clifford@clifford.at> | 2013-03-31 11:19:11 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-03-31 11:19:11 +0200 |
commit | 161565be104fd0c7b7c4224bd23e9502625e041a (patch) | |
tree | f0c54a731d73dc7b334579acb56950497a9e1cb6 /frontends | |
parent | 5640b7d6078a681e33e85f06920394204f41c875 (diff) | |
download | yosys-161565be104fd0c7b7c4224bd23e9502625e041a.tar.gz yosys-161565be104fd0c7b7c4224bd23e9502625e041a.tar.bz2 yosys-161565be104fd0c7b7c4224bd23e9502625e041a.zip |
Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
Diffstat (limited to 'frontends')
-rw-r--r-- | frontends/ast/ast.cc | 9 | ||||
-rw-r--r-- | frontends/ast/ast.h | 1 | ||||
-rw-r--r-- | frontends/ast/genrtlil.cc | 4 | ||||
-rw-r--r-- | frontends/ast/simplify.cc | 2 | ||||
-rw-r--r-- | frontends/verilog/parser.y | 2 |
5 files changed, 15 insertions, 3 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 091b196ef..391e0a444 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -122,6 +122,7 @@ std::string AST::type2str(AstNodeType type) X(AST_CELL) X(AST_PRIMITIVE) X(AST_ALWAYS) + X(AST_INITIAL) X(AST_BLOCK) X(AST_ASSIGN_EQ) X(AST_ASSIGN_LE) @@ -417,6 +418,14 @@ void AstNode::dumpVlog(FILE *f, std::string indent) } break; + case AST_INITIAL: + fprintf(f, "%s" "initial\n", indent.c_str()); + for (auto child : children) { + if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE) + child->dumpVlog(f, indent + " "); + } + break; + case AST_POSEDGE: case AST_NEGEDGE: case AST_EDGE: diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 05b9a95cf..918f12c1a 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -103,6 +103,7 @@ namespace AST AST_CELL, AST_PRIMITIVE, AST_ALWAYS, + AST_INITIAL, AST_BLOCK, AST_ASSIGN_EQ, AST_ASSIGN_LE, diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 47ca37bd0..2f5370fe8 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -310,6 +310,7 @@ struct AST_INTERNAL::ProcessGenerator case AST_COND: case AST_ALWAYS: + case AST_INITIAL: for (auto child : ast->children) if (child->type == AST_BLOCK) collect_lvalues(reg, child, type_eq, type_le, false); @@ -1013,7 +1014,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint) break; // use ProcessGenerator for always blocks - case AST_ALWAYS: { + case AST_ALWAYS: + case AST_INITIAL: { AstNode *always = this->clone(); ProcessGenerator generator(always); delete always; diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index a03cd0bed..fbbe66ed3 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -196,7 +196,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage) current_block = this; current_block_child = children[i]; } - if (type == AST_ALWAYS && children[i]->type == AST_BLOCK) + if ((type == AST_ALWAYS || type == AST_INITIAL) && children[i]->type == AST_BLOCK) current_top_block = children[i]; did_something_here = children[i]->simplify(const_fold_here, at_zero, in_lvalue_here, stage); if (did_something_here) diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y index 9caa236f8..22af178e8 100644 --- a/frontends/verilog/parser.y +++ b/frontends/verilog/parser.y @@ -607,7 +607,7 @@ always_stmt: ast_stack.pop_back(); } | attr TOK_INITIAL { - AstNode *node = new AstNode(AST_ALWAYS); + AstNode *node = new AstNode(AST_INITIAL); append_attr(node, $1); ast_stack.back()->children.push_back(node); ast_stack.push_back(node); |