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| author | Clifford Wolf <clifford@clifford.at> | 2013-07-07 16:49:30 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-07-07 16:49:30 +0200 |
| commit | e8da3ea7b647f2c1eeba8a84590df7b05ca4e046 (patch) | |
| tree | 61d47e86a00eedaa597129a8d161b69832e5d1d0 /frontends | |
| parent | eff68560a2914791c8d0377edb5922fd5077f4f3 (diff) | |
| download | yosys-e8da3ea7b647f2c1eeba8a84590df7b05ca4e046.tar.gz yosys-e8da3ea7b647f2c1eeba8a84590df7b05ca4e046.tar.bz2 yosys-e8da3ea7b647f2c1eeba8a84590df7b05ca4e046.zip | |
Fixed another bug found using vloghammer
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 03bb8a430..f9f5c6f88 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -798,7 +798,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint) if (0) { case AST_SHIFT_SLEFT: type_name = "$sshl"; is_signed = true; } if (0) { case AST_SHIFT_SRIGHT: type_name = "$sshr"; is_signed = true; } { - RTLIL::SigSpec left = children[0]->genRTLIL(width_hint); + RTLIL::SigSpec left = children[0]->genRTLIL(); RTLIL::SigSpec right = children[1]->genRTLIL(width_hint); int width = width_hint > 0 ? width_hint : left.width; return binop2rtlil(this, type_name, width, left, right); |