| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 6 | -4/+40 |
| * | Add support for SystemVerilog unique, unique0, and priority case | Clifford Wolf | 2017-02-23 | 2 | -4/+25 |
| * | Preserve string parameters | Clifford Wolf | 2017-02-23 | 1 | -2/+8 |
| * | Added SystemVerilog support for ++ and -- | Clifford Wolf | 2017-02-23 | 2 | -1/+12 |
| * | Fix incorrect "incompatible re-declaration of wire" error in tasks/functions | Clifford Wolf | 2017-02-14 | 1 | -2/+9 |
| * | Add support for verific mem initialization | Clifford Wolf | 2017-02-11 | 1 | -0/+38 |
| * | Fix another stupid bug in the same line | Clifford Wolf | 2017-02-11 | 1 | -1/+1 |
| * | Add verific support for initialized variables | Clifford Wolf | 2017-02-11 | 1 | -3/+47 |
| * | Improve handling of Verific warnings and error messages | Clifford Wolf | 2017-02-11 | 1 | -4/+10 |
| * | Fix extremely stupid typo | Clifford Wolf | 2017-02-11 | 1 | -1/+1 |
| * | Add checker support to verilog front-end | Clifford Wolf | 2017-02-09 | 2 | -11/+24 |
| * | Add "rand" and "rand const" verific support | Clifford Wolf | 2017-02-09 | 1 | -0/+41 |
| * | Add SV "rand" and "const rand" support | Clifford Wolf | 2017-02-08 | 2 | -8/+28 |
| * | Add PSL parser mode to verific front-end | Clifford Wolf | 2017-02-08 | 1 | -2/+17 |
| * | Add "read_blif -wideports" | Clifford Wolf | 2017-02-06 | 2 | -5/+77 |
| * | Further improve cover() support | Clifford Wolf | 2017-02-04 | 1 | -0/+6 |
| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 7 | -5/+16 |
| * | Add assert/assume support to verific front-end | Clifford Wolf | 2017-02-04 | 2 | -625/+687 |
| * | Add "enum" and "typedef" lexer support | Clifford Wolf | 2017-01-17 | 2 | -1/+4 |
| * | Fix bug in AstNode::mem2reg_as_needed_pass2() | Clifford Wolf | 2017-01-15 | 1 | -0/+2 |
| * | Fixed handling of local memories in functions | Clifford Wolf | 2017-01-05 | 1 | -2/+2 |
| * | Added handling of local memories and error for local decls in unnamed blocks | Clifford Wolf | 2017-01-04 | 1 | -1/+10 |
| * | Added Verilog $rtoi and $itor support | Clifford Wolf | 2017-01-03 | 1 | -24/+30 |
| * | Added "verilog_defines" command | Clifford Wolf | 2016-12-15 | 1 | -0/+60 |
| * | Added support for macros as include file names | Clifford Wolf | 2016-11-28 | 1 | -0/+2 |
| * | Bugfix in "read_verilog -D NAME=VAL" handling | Clifford Wolf | 2016-11-28 | 1 | -3/+3 |
| * | Added support for hierarchical defparams | Clifford Wolf | 2016-11-15 | 3 | -16/+41 |
| * | Remember global declarations and defines accross read_verilog calls | Clifford Wolf | 2016-11-15 | 4 | -7/+19 |
| * | Fixed anonymous genblock object names | Clifford Wolf | 2016-11-04 | 1 | -1/+1 |
| * | Some fixes in handling of signed arrays | Clifford Wolf | 2016-11-01 | 2 | -0/+7 |
| * | Added avail params to ilang format, check module params in 'hierarchy -check' | Clifford Wolf | 2016-10-22 | 2 | -3/+14 |
| * | No limit for length of lines in BLIF front-end | Clifford Wolf | 2016-10-19 | 1 | -1/+7 |
| * | Added $anyseq cell type | Clifford Wolf | 2016-10-14 | 3 | -5/+5 |
| * | Added $global_clock verilog syntax support for creating $ff cells | Clifford Wolf | 2016-10-14 | 3 | -5/+19 |
| * | Added $ff and $_FF_ cell types | Clifford Wolf | 2016-10-12 | 1 | -4/+8 |
| * | Added liberty parser support for types within cell decls | Clifford Wolf | 2016-09-23 | 1 | -39/+46 |
| * | Added $past, $stable, $rose, $fell SVA functions | Clifford Wolf | 2016-09-19 | 2 | -2/+141 |
| * | Added support for bus interfaces to "read_liberty -lib" | Clifford Wolf | 2016-09-18 | 1 | -1/+77 |
| * | Added assertpmux | Clifford Wolf | 2016-09-07 | 1 | -0/+1 |
| * | Bugfix in parsing of BLIF latch init values | Clifford Wolf | 2016-09-06 | 1 | -1/+1 |
| * | Avoid creation of bogus initial blocks for assert/assume in always @* | Clifford Wolf | 2016-09-06 | 3 | -1/+13 |
| * | Added $anyconst support to yosys-smtbmc | Clifford Wolf | 2016-08-30 | 1 | -0/+2 |
| * | Removed $aconst cell type | Clifford Wolf | 2016-08-30 | 3 | -6/+6 |
| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 6 | -14/+3 |
| * | Added read_verilog -norestrict -assume-asserts | Clifford Wolf | 2016-08-26 | 4 | -5/+40 |
| * | Improved verilog parser errors | Clifford Wolf | 2016-08-25 | 1 | -0/+3 |
| * | Added SV "restrict" keyword | Clifford Wolf | 2016-08-24 | 1 | -1/+2 |
| * | Fixed bug with memories that do not have a down-to-zero data width | Clifford Wolf | 2016-08-22 | 1 | -2/+13 |
| * | Another bugfix in mem2reg code | Clifford Wolf | 2016-08-21 | 3 | -7/+31 |
| * | Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog() | Clifford Wolf | 2016-08-21 | 1 | -4/+15 |
