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| author | Clifford Wolf <clifford@clifford.at> | 2017-02-09 12:53:46 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-02-09 12:53:46 +0100 |
| commit | 2ca8d483dde46e72f17f862ca117e2dd944e9709 (patch) | |
| tree | 87b0650170cc0b861812e510ea0dd67fb7610da1 /frontends | |
| parent | ef4a28e112be10d3d62395f68e53e8b7e42dbf68 (diff) | |
| download | yosys-2ca8d483dde46e72f17f862ca117e2dd944e9709.tar.gz yosys-2ca8d483dde46e72f17f862ca117e2dd944e9709.tar.bz2 yosys-2ca8d483dde46e72f17f862ca117e2dd944e9709.zip | |
Add "rand" and "rand const" verific support
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verific/verific.cc | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index f3b997dc5..3f5cf3f5f 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -617,6 +617,9 @@ struct VerificImporter module->fixup_ports(); + pool<Net*, hash_ptr_ops> anyconst_nets; + pool<Net*, hash_ptr_ops> anyseq_nets; + FOREACH_NET_OF_NETLIST(nl, mi, net) { if (net->IsRamNet()) @@ -646,6 +649,15 @@ struct VerificImporter continue; } + const char *rand_const_attr = net->GetAttValue(" rand_const"); + const char *rand_attr = net->GetAttValue(" rand"); + + if (rand_const_attr != nullptr && !strcmp(rand_const_attr, "1")) + anyconst_nets.insert(net); + + else if (rand_attr != nullptr && !strcmp(rand_attr, "1")) + anyseq_nets.insert(net); + if (net_map.count(net)) { // log(" skipping net %s.\n", net->Name()); continue; @@ -700,8 +712,37 @@ struct VerificImporter { // log(" skipping netbus %s.\n", netbus->Name()); } + + SigSpec anyconst_sig; + SigSpec anyseq_sig; + + for (int i = netbus->RightIndex();; i += netbus->IsUp() ? -1 : +1) { + net = netbus->ElementAtIndex(i); + if (net != nullptr && anyconst_nets.count(net)) { + anyconst_sig.append(net_map.at(net)); + anyconst_nets.erase(net); + } + if (net != nullptr && anyseq_nets.count(net)) { + anyseq_sig.append(net_map.at(net)); + anyseq_nets.erase(net); + } + if (i == netbus->LeftIndex()) + break; + } + + if (GetSize(anyconst_sig)) + module->connect(anyconst_sig, module->Anyconst(NEW_ID, GetSize(anyconst_sig))); + + if (GetSize(anyseq_sig)) + module->connect(anyseq_sig, module->Anyseq(NEW_ID, GetSize(anyseq_sig))); } + for (auto net : anyconst_nets) + module->connect(net_map.at(net), module->Anyconst(NEW_ID)); + + for (auto net : anyseq_nets) + module->connect(net_map.at(net), module->Anyseq(NEW_ID)); + FOREACH_INSTANCE_OF_NETLIST(nl, mi, inst) { if (inst->Type() == PRIM_SVA_POSEDGE) { |