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* sv: support declaration in generate for initializationZachary Snow2021-08-311-1/+95
* sv: support declaration in procedural for initializationZachary Snow2021-08-301-1/+48
* sv: improve support for wire and var with user-defined typesBrett Witherspoon2021-08-121-11/+44
* Allow optional comma after last entry in enumMichael Singer2021-08-091-11/+12
* verilog: Support tri/triand/trior wire types.Marcelina Kościelnicka2021-08-061-0/+3
* verilog: save and restore overwritten macro argumentsZachary Snow2021-07-282-4/+31
* Add support for parsing the SystemVerilog 'bind' constructRupert Swarbrick2021-07-162-3/+75
* sv: fix a few struct and enum memory leaksZachary Snow2021-07-061-2/+4
* sv: fix up end label checkingZachary Snow2021-06-161-7/+18
* verilog: fix leaking of type names in parserXiretza2021-06-141-0/+2
* verilog: fix wildcard port connections leaking memoryXiretza2021-06-141-0/+1
* verilog: fix leaking ASTNodesXiretza2021-06-141-7/+10
* verilog: Squash a memory leak.Marcelina Kościelnicka2021-06-144-19/+14
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-087-7/+7
* sv: support tasks and functions within packagesZachary Snow2021-06-011-1/+1
* sv: support remaining assignment operatorsZachary Snow2021-05-252-42/+41
* sv: check validity of package end labelZachary Snow2021-05-101-0/+2
* verilog: revise hot comment warningsZachary Snow2021-03-301-6/+21
* preproc: Fix up conditional handling.Marcelina Kościelnicka2021-03-301-3/+17
* verilog: check entire user type stack for type definitionXiretza2021-03-211-6/+12
* sv: allow typenames as function return typesZachary Snow2021-03-191-0/+6
* verilog: rebuild user_type_stack from globals before parsing fileXiretza2021-03-181-5/+21
* sv: carry over global typedefs from previous filesZachary Snow2021-03-171-2/+5
* sv: support for parameters without default valuesZachary Snow2021-03-021-3/+21
* verilog: fix sizing of ports with int types in module headersZachary Snow2021-03-011-2/+3
* verilog: fix handling of nested ifdef directivesZachary Snow2021-03-011-11/+38
* Merge pull request #2523 from tomverbeure/define_synthesisClaire Xen2021-03-011-3/+12
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| * Fix indents.Tom Verbeure2021-01-041-2/+2
| * Add -nosynthesis flag for read_verilog command.Tom Verbeure2021-01-041-3/+12
* | sv: extended support for integer typesZachary Snow2021-02-282-39/+70
* | Fix handling of unique/unique0/priority cases in the frontend.Marcelina Kościelnicka2021-02-252-15/+16
* | Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and tu...TimRudy2021-02-241-2/+7
* | verilog: error on macro invocations with missing argument listsZachary Snow2021-02-191-1/+10
* | Merge pull request #2578 from zachjs/genblk-portZachary Snow2021-02-111-4/+7
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| * | verlog: allow shadowing module ports within generate blocksZachary Snow2021-02-071-4/+7
* | | Add missing is_signed to type_atomKamil Rakoczy2021-02-111-4/+4
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* | Add check of begin/end labels for genblockKamil Rakoczy2021-02-041-0/+2
* | Merge pull request #2529 from zachjs/unnamed-genblkwhitequark2021-02-041-17/+28
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| * | verilog: significant block scoping improvementsZachary Snow2021-01-311-17/+28
* | | verilog: strip leading and trailing spaces in macro argsZachary Snow2021-01-281-1/+5
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* | Merge pull request #2550 from zachjs/macro-arg-spaceswhitequark2021-01-251-1/+0
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| * | verilog: allow spaces in macro argumentsZachary Snow2021-01-201-1/+0
* | | Allow combination of rand and const modifiersZachary Snow2021-01-211-2/+10
* | | sv: fix support wire and var data type modifiersZachary Snow2021-01-201-9/+23
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* / Parse package user type in module port listLukasz Dalek2021-01-181-30/+32
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* sv: complete support for implied task/function port directionsZachary Snow2020-12-311-0/+10
* Fix SYNTHESIS always being defined in Verilog frontendgeorgerennie2020-12-012-1/+3
* Ignore empty parameters in Verilog module instantiationsClaire Xenia Wolf2020-10-011-0/+3
* Rewrite multirange arrays sizes [n] as [n-1:0]Lukasz Dalek2020-08-031-2/+11
* Treat all bison warnings as errors in verilog front-endClaire Wolf2020-07-151-1/+1
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