| Commit message (Expand) | Author | Age | Files | Lines |
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| * | verilog_lexer: Increase YY_BUF_SIZE to 65536 | David Shah | 2019-07-26 | 1 | -0/+3 |
| * | Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/Symbi... | Clifford Wolf | 2019-07-02 | 1 | -0/+2 |
| * | Fixed brojen $error()/$info/$warning() on non-generate blocks | Udi Finkelstein | 2019-06-11 | 1 | -1/+1 |
| * | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo... | Clifford Wolf | 2019-06-07 | 1 | -0/+5 |
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| | * | Initial implementation of elaboration system tasks | Udi Finkelstein | 2019-05-03 | 1 | -0/+5 |
| * | | Merge branch 'master' into wandwor | Stefan Biereigel | 2019-05-27 | 1 | -1/+1 |
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| | * | | Added support for unsized constants, fixes #1022 | Miodrag Milanovic | 2019-05-27 | 1 | -1/+1 |
| * | | | make lexer/parser aware of wand/wor net types | Stefan Biereigel | 2019-05-23 | 1 | -0/+2 |
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| * | | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify | Clifford Wolf | 2019-05-06 | 1 | -0/+2 |
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| | * \ | Merge pull request #988 from YosysHQ/clifford/fix987 | Clifford Wolf | 2019-05-04 | 1 | -0/+1 |
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| | | * | | Add approximate support for SV "var" keyword, fixes #987 | Clifford Wolf | 2019-05-04 | 1 | -0/+1 |
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| | * / | Add support for SVA "final" keyword | Clifford Wolf | 2019-05-04 | 1 | -0/+1 |
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| * | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -1/+1 |
| * | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 1 | -0/+11 |
| * | | Un-break default specify parser | Clifford Wolf | 2019-04-23 | 1 | -0/+1 |
| * | | Add specify parser | Clifford Wolf | 2019-04-23 | 1 | -1/+6 |
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| * | Fix handling of cases that look like sva labels, fixes #862 | Clifford Wolf | 2019-03-10 | 1 | -49/+10 |
| * | Also add support for labels on sva module items, fixes #699 | Clifford Wolf | 2019-03-08 | 1 | -5/+52 |
| * | Bugfix in Verilog string handling | Clifford Wolf | 2019-01-05 | 1 | -1/+1 |
| * | Merge pull request #659 from rubund/sv_interfaces | Clifford Wolf | 2018-10-18 | 1 | -0/+8 |
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| | * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -0/+8 |
| * | | ignore protect endprotect | argama | 2018-10-16 | 1 | -0/+3 |
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| * | Add "make coverage" | Clifford Wolf | 2018-08-27 | 1 | -1/+1 |
| * | Merge pull request #513 from udif/pr_reg_wire_error | Clifford Wolf | 2018-08-15 | 1 | -1/+1 |
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| | * | This PR should be the base for discussion, do not merge it yet! | Udi Finkelstein | 2018-03-11 | 1 | -1/+1 |
| * | | Support more character literals | Dan Gisselquist | 2018-05-03 | 1 | -1/+9 |
| * | | First draft of Verilog parser support for specify blocks and parameters. | Udi Finkelstein | 2018-03-27 | 1 | -0/+3 |
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| * | Add Verilog "automatic" keyword (ignored in synthesis) | Clifford Wolf | 2017-11-23 | 1 | -0/+1 |
| * | Fix ignoring of simulation timings so that invalid module parameters cause sy... | Clifford Wolf | 2017-09-26 | 1 | -4/+0 |
| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 1 | -0/+3 |
| * | Add support for SystemVerilog unique, unique0, and priority case | Clifford Wolf | 2017-02-23 | 1 | -0/+4 |
| * | Added SystemVerilog support for ++ and -- | Clifford Wolf | 2017-02-23 | 1 | -1/+3 |
| * | Add checker support to verilog front-end | Clifford Wolf | 2017-02-09 | 1 | -9/+11 |
| * | Add SV "rand" and "const rand" support | Clifford Wolf | 2017-02-08 | 1 | -2/+4 |
| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 1 | -0/+1 |
| * | Add "enum" and "typedef" lexer support | Clifford Wolf | 2017-01-17 | 1 | -0/+3 |
| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 1 | -1/+0 |
| * | Added read_verilog -norestrict -assume-asserts | Clifford Wolf | 2016-08-26 | 1 | -1/+1 |
| * | Added SV "restrict" keyword | Clifford Wolf | 2016-08-24 | 1 | -1/+2 |
| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 1 | -1/+5 |
| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 1 | -0/+1 |
| * | Added support for SystemVerilog packages with localparam definitions | Ruben Undheim | 2016-06-18 | 1 | -0/+4 |
| * | SystemVerilog also has assume(), added implicit -D FORMAL | Clifford Wolf | 2015-10-13 | 1 | -1/+1 |
| * | Fixed support for $write system task | Clifford Wolf | 2015-09-23 | 1 | -1/+1 |
| * | Another block of spelling fixes | Larry Doolittle | 2015-08-14 | 1 | -2/+2 |
| * | Adjust makefiles to work with out-of-tree builds | Clifford Wolf | 2015-08-12 | 1 | -1/+1 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -2/+2 |
| * | Ignore celldefine directive in verilog front-end | Clifford Wolf | 2015-03-25 | 1 | -0/+3 |
| * | Added non-std verilog assume() statement | Clifford Wolf | 2015-02-26 | 1 | -2/+3 |
| * | Fixed handling of "//" in filenames in verilog pre-processor | Clifford Wolf | 2015-02-14 | 1 | -0/+4 |
